9:00 a.m. to 10:00 a.m. |
PCEA Annual Meeting
Stephen Chavez, Siemens
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10:00 a.m. to 12:00 p.m. |
1. Principles of Building a PCB Stackup
Susy Webb, Design Science
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10:00 a.m. to 12:00 p.m. |
2. Improving Circuit Design and Layout for Accessibility and Success
Tomas Chester, Chester Electronic Designs
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10:00 a.m. to 12:00 p.m. |
3. Avoiding PCB Respins, Reducing Cost and Time to Market
Syed Ubaid Ali Warsi, Wavetroniks
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10:00 a.m. to 12:00 p.m. |
4. Mixed Signal Noise Sources and Solutions
Keven Coates, Fluidity Technologies
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10:00 a.m. to 12:00 p.m. |
5. Benefits of Signal and Power Simulations for PCB DDR Traces
Ramon Angelo Martin Lardizabal, Analog Devices
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10:00 a.m. to 5:00 p.m. |
6. Power Delivery System (PDS) Design
Lee Ritchey, Speeding Edge
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10:00 a.m. to 5:00 p.m. |
7. Sintered Vias for HDI PCB Design
Sean Ernest Clyde Nodado, Analog Devices
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12:00 p.m. to 1:00 p.m. |
Free Lunch-and-Learn for Conference Registrants
|
1:30 p.m. to 3:30 p.m. |
8. PCB DfM (A Comedy Routine Depicting a Typical Dialogue between a PCB Designer and Fabricator)
Stephen Chavez, Siemens, and Gerry Partida, Summit Interconnect
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1:30 p.m. to 3:30 p.m. |
9. Ask the Flexperts with Lessons Learned
Mark Finstad, Flexible Circuit Technologies, and Nick Koop, TTM Technologies
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1:30 p.m. to 5:00 p.m. |
10. Signal Integrity in Thin PCB Materials
Zachariah Peterson, Northwest Engineering Solutions
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1:30 p.m. to 5:00 p.m. |
11. Parts Placement Choices and Consequences
Susy Webb, Design Science
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1:30 p.m. to 5:00 p.m. |
12. Circuit Grounding to Control Noise and EMI
Rick Hartley, RHartley Enterprises
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1:30 p.m. to 5:00 p.m. |
13. PCB Design for High Reliability
Paul Cooke, Ventec
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3:30 p.m. to 5:30 p.m. |
14. Design with the End in Mind: Using System Level Simulation to Reduce PCB Field Failures
Harry Kennedy Jr., Altair
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