2020 Conference Program

10:00 a.m. – 6:00 p.m.
1: The Basics of PCB Design
Speaker: Susy Webb, Design Science

Technical sessions at conferences often emphasize the latest techniques and technologies, but those classes are often too in-depth for a novice designer, and don’t speak to the questions from the engineers who need to design their own boards. This class features an overview of the entire process of designing a board, from start to finish. We will begin with creating manufacturable footprints that meet the IPC specs. Then we will address some common placement techniques like floor planning, color-coding, flow, orientation, and placement to set up routing. We will follow that with a discussion of planes and stackups and how to configure them to get the best results for parts and signals. Next, we move on to some fanout and routing techniques that are helpful for completing the design connections to meet the number one design rule: good electrical performance. We will complete the process by discussing some manufacturability concerns that can be affected by the way the board is designed, some finishing issues, and sending out good documentation that the manufacturers can easily understand and use.

Who should attend: PCB Designer/Design Engineer
Target audience: Beginner, Intermediate

10:00 a.m. – 6:00 p.m.
2: A Practical Guide to RF and Microwave PCB Design
Speaker: Benjamin Jordan, Altium

This is a session for embedded engineers and PCB designers who have never done RF board layout but are curious and want to have a go at it. It is not for experienced microwave engineers. This practical workshop will introduce (or reintroduce) basic math associated with the topic, but the goal is to be practical and intuitive, not theoretical and esoteric. We will visualize the elements available and build and test using desktop prototyping gear.

The class is broken into two sessions (morning and afternoon). Session 1: Back to basics electromagnetic recap; transmission lines – what you need to know; EM and T-line visualizations; PCB materials and conductors for RF and microwave. Session 2: Essential transmission line evaluation skills (VSWR, S-parameters, basic simulation and visualization); introduction to the Smith chart, and how to match impedance; practical design exercise with introduction to the VNA; using the desktop CNC to mill practical prototypes (and tips to mill with accuracy); introduction to PCB antenna types.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate

10:00 a.m. – 5:00 p.m.
3: Printed Circuit Board Stackup Design for High-Performance Products
Speaker: Lee Ritchey, Speeding Edge

This comprehensive seminar of how to design a PCB stackup to optimize performance while attaining the lowest cost possible. With the advent of very high-speed signaling along with multiple very high-current power supply rails, it is necessary to understand how materials behave and how PCBs are fabricated in order to arrive at a PCB stackup that results in a “right the first time” design. The seminar draws from the speaker’s long experience designing PCB stackup for products ranging from video games to supercomputers. It draws on the results of dozens of test PCBs used to characterize materials from a loss and high-speed skew perspective.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced

10:00 a.m. – 12:00 noon
4: Differential Pair Routing for SI and EMI Control
Speaker: Rick Hartley, RHartley Enterprises

Differential pairs have been used in PC boards for years to carry high-speed serial and high-speed parallel data, in a variety of bus formats. Many board designers and engineers believe the rules for differential pairs are the same in a PCB as they are in cable or twisted pairs of wires. This is usually not the case!

This course will cover the advantages of differential pairs vs. single-ended lines, which differential pair format gives the best impedance control, what is the right spacing between the lines of a pair, crosstalk between differential pairs, what is important in differential pair routing, how much timing skew is really acceptable, the impact of material type and the impact of vias on signal integrity and EMI.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate

10:00 a.m. – 12:00 noon
5: Semi-Additive PCB Processing Resets the Technology Curve
Speaker: Mike Vinson, Averatek, and Kelly Dack, KeyTronic

The continued miniaturization of both packaging and component size in next-generation electronics presents a challenge for PCB designers to effectively navigate the constraints of the traditional subtractive etch PCB fabrication processes and contribute to the need for finer feature size, higher layer count, stacked microvias and increased lamination cycles. Semi-Additive PCB processes provide an alternative that effectively resets the technology curve while increasing reliability.

The ability to design with and manufacture a 25-micron trace and space repeatedly and reliably provides options and opportunities previously not available to PCB designers. While just scratching the surface, the ability to reduce the number of layers needed for routing high-density BGAs, increase hole size, reduce the number of micro via layers required, dramatically reduce size, weight and packaging and conversely increase the electronic content within an existing footprint are benefits being explored and realized as these feature sizes are being applied to new PCB designs.

This session will explain the science and technology behind the semi-additive process and how this process is currently being integrated with traditional subtractive etch chemistries and equipment. As with any emerging technology, there are many questions. The session will continue by addressing frequently asked questions from both a fabrication and design perspective. Once the fundamentals of the process are understood, the session will continue with use cases showing various ways that this technology can be applied to PCB designs. Examples provided will include a starting point with traditional design rules, highlight various ways that a 25-micron trace and space capability could be applied and demonstrate resulting benefits to layer count, size and overall complexity.

Time will be allocated for specific questions and overall industry discussion around semi-additive processes, how they integrate with subtractive etch processing and potential benefits.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate, Advanced

10:00 a.m. – 12:00 noon
6: Causes of Signal Degradation in PCB Transmission Lines
Speaker: Atar Mittal, Sierra Circuits

Signal degradation on PCB transmission lines manifests in many forms: undershoot, overshoot, ringing, pulse shape distortion, switching noise, attenuation, ground bounce, skew, etc. All these can be attributed to one or more of these sources: signal reflections caused by characteristic impedance discontinuities; signal distortion due to conductor and dielectric losses resulting from PCB materials’ properties as signals travel over the transmission lines; crosstalk from signals on nearby PCB conductors; noise in power distribution network; electromagnetic interference (EMI). Impedance discontinuities manifest from many sources, to name a few: unmatched loads and terminations, non-uniformity in the lines, vias, stubs, component and test pads, gaps in reference planes and poorly designed return paths, stray capacitances and inductances, and branching of signal paths, and all these cause signal reflections. Frequency dependence of the copper and dielectric losses cause unequal attenuation of various frequency contents in the signals, causing signal rise time degradation, and variations in dielectric constant with frequency cause different frequency signal components traveling at different speeds.

Crosstalk from nearby conductors occurs due to inductive and capacitive coupling, causing several issues: near- and far-end crosstalk, switching noise, ground bounce, etc. PDN noise and unwanted electromagnetic energy will superimpose on signals causing signal integrity issues. After identifying the root cause, one can find solutions to the signal integrity problem.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Intermediate

12:00 noon – 1:00 p.m.
LUNCH and LEARN, Sponsored by Summit Interconnect
1:00 p.m. – 3:00 p.m.
7: From Smart Factory Automation to Digital Twin Standard: Ushering a New Era for Design and Manufacturing
Speaker: Michael Ford, Aegis Software, and Hemant Shah, Cadence

The new IPC Digital Twin standard (IPC-2551) defines an interoperable framework in which thousands of applications from multiple sources work seamlessly together, providing the opportunity for virtual prototyping of all aspects of design, manufacturing and beyond. Use of IPC-2551 prevents companies in all areas of the industry from making the mistake of tying themselves to any monopolistic data exchange technology. The impact of the IPC Digital Twin on the design through manufacturing flow will be significant, and will be the area that develops sooner than any other, built upon and driven by existing IPC standards, such as IPC-2581 (DPMX), IPC-2591 (CfX) and IPC-1782 internal and external (secure supply-chain) traceability. This presentation explains the IPC Digital Twin standard, using some specific use-case examples that illustrate the value and opportunity that the standard provides to both the design and manufacturing communities, exchanging digital models bidirectionally between design and manufacturing. This presentation will be of critical interest to all of those involved in design and manufacturing, including business management, engineers and technology providers.

Who should attend: CB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced

1:00 p.m. – 4:30 p.m.
8: IoT PC Board Design and Layout
Speaker: Rick Hartley, RHartley Enterprises

Circuit boards for the IoT world (Internet of Things) are often driven by the need for low power dissipation, low cost (which drives very low layer count), moderate to high-density and mixed-signal applications. This combination of needs can make board design an extreme challenge. Creating a 1-, 2- or 4-layer board, with excellent signal integrity and low noise/interference and no EMI issues can, by itself, be a very serious challenge. This 3.5-hour course will discuss how to understand when it is necessary to control impedance of lines, how to do it cost-effectively, proper setup of routed lines to keep circuit energy from spreading (preventing interference), even on a one layer board, design of antenna into the PCB, circuit grounding in low layer count boards, power distribution without the benefit of power planes, ground bounce, cross talk with low layer count and design to optimize manufacturability of low layer count PCBs.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate

1:00 p.m. – 4:30 p.m.
9: Flexible Circuits: Design Through Test with Lessons Learned
Speaker: Mark Finstad, Flexible Circuit Technologies and Nick Koop, TTM Technologies

This course will cover the entire gamut of flexible and rigid-flex circuits from two of the most recognized names in the flexible circuit industry: Mark Finstad (co-chair of IPC-2223) and Nick Koop (co-chair of IPC-6013). Topics covered will include mechanical design/material selection, cost drivers, bending and forming concerns, testing, and issues unique to rigid-flex. This course also includes a complete virtual plant tour of a flexible circuit manufacturing facility to help attendees understand the manufacturing processes. Throughout the presentation, the instructors will share real-life stories of flexible circuit applications gained over 35+ years in the industry. Some are success stories, others not so much, but all provide excellent lessons learned. The instructors also welcome and encourage questions and enjoy wandering off-course with lively interactive discussions on specific topics from the class.

Who should attend: PCB Designer/Design Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate

1:00 p.m. – 4:30 p.m.
10: Effective PCB Design: Techniques to Improve Performance
Speaker: Daniel Beeker, NXP Semiconductor

Tired of failing EMC certification over and over? Join the crowd. Shrinking IC geometries and a resulting increase in switching speeds make designing compliant printed circuit boards more challenging than ever. We need a new design methodology to change this unacceptable status quo, one based on electromagnetic field physics. This training module presents a basic introduction to EM fields and provides guidelines for building successful, cost-effective printed circuit boards. This presentation includes example designs and test results.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced

3:00 p.m. – 5:00 p.m.
11: Next-Generation Materials: High-Speed, RF and HDI Designs
Speaker: Michael R. Creeden, CID+, Insulectro

With this presentation, attendees will learn how materials matter in the 5G-world. From rigid laminates, copper styles and properties, flex materials, sintered paste OrMet for any-layer vias: all play a part of the design, manufacturing and performance of products. Attendees will receive a good understanding of basic EM theory, with a strong emphasis on material selection. This will cover aspects affecting interconnections and their respective EM fields. The design flow is from the start of the layout cycle all the way to the generation of deliverables and then into manufacturing. Emphasis is on the role that materials play to make a circuit cost-effective, perform well and be a reliable high-yield product. We will touch on all types of circuit technologies in many market segments. Focus is on integration between design and manufacturing early in the development cycle, to build a high-reliability product that is correct-by-construction and performs on Revision-1.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate, Advanced

6:00 p.m. – 8:00 p.m.
Printed Circuit Engineers Association Meeting
10:00 a.m. – 2:00 p.m.
Booth Barista sponsored by Zuken
10:00 a.m. – 2:30 p.m.
12: Embedded Capacitance Technology Concept: Design, Implementation, and Processing Guidelines
Speakers: Robert Carter, Oak-Mitsui Technologies, and Benjamin Jordan, Altium

Large data transmission continues to increase annually due to live video streaming, cloud storage, PDA usage, IOT, and other technologies. Electronic devices are getting smaller, yet are required to accommodate higher speeds and good signal/power integrity. One solution to this emerging technological challenge is embedded capacitance technology. Planar embedded capacitance will reduce overall inductance of the power distribution network and free surface real estate by removing discrete capacitors. Ultra-thin laminates with high capacitance and Dk will also help reduce noise. Additionally, embedded capacitance technology offers better reliability due to having fewer components on the PCB surface. The course will cover important aspects of utilizing embedded capacitance technology in order to enhance PCB design. Course outline: 1. Benefits of embedded capacitance technology. How does it work? 2. Times to consider using embedded capacitance technology. Utilizing simulation tools to see benefits. Real-world case studies 3. Implementing embedded capacitance with a CAD tool schematic and layout. Changing existing design to include embedded capacitance. New design with embedded capacitance 4. Processing guidelines.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced

10:00 a.m. – 12:00 p.m.
13: RF and Mixed Signal PCB Layout
Speaker: Rick Hartley, RHartley Enterprises

This session is intended for board designers to understand the things RF engineers request during PCB layout. Experienced RF engineers will likely not learn anything new from this course, as the material is mainly geared to board designers.

Due to sensitivity in analog circuits, the keys to full functionality (whether you are designing very high-frequency analog PC boards, mixing RF with digital or mixing low-frequency analog with digital) are signal integrity and noise control in the design of the printed circuit board. This course will cover differences between analog and digital, circuit changes over time, lumped vs. distributed length lines, reflections/return loss/VSWR, low- and high-frequency current, transmission line behavior, impedance control, microstrip vs. stripline, coplanar waveguide w/ ground, circuit termination, 1/4 wavelength couplers and filters designed into board copper, layout techniques and strategies, critical routing and circuit isolation, ground plane splitting (when to and when not to), mismatched loads and other discontinuities, signal splitters, tuning transmission lines, power bus decoupling for RF vs. digital circuits and board stack-ups for mixed RF and digital circuits.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Intermediate

10:00 a.m. – 12:00 p.m.
14: An Intuitive Approach to Understanding Basic High-Speed Layout
Speaker: Keven Coates, Geospace Technologies

What is a wire? At high speeds, it behaves very differently from what we were taught in college. This presentation on high-speed basics makes the subject intuitive in a way that’s easily understood. Learn about how frequency enters the picture, high-speed signal propagation, impedance, noise, and reflections with easy-to-understand animations and analogies to understand this subject on a deeper level.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner

10:00 a.m. – 12:00 p.m.
15: From DC to AC – Power Integrity and Decoupling Primer for PCB Designers
Speaker: Ralf Bruening, Zuken

Supply voltages decrease with every new silicon generation, contributing as well to the goal of reducing power consumption of our electronics. Coupled with the resulting shrinking noise margins for these ICs, this defines increasing demands for the quality and stability of power distribution schemes of PCBs. Hence, tighter requirements and constraints from silicon vendors are defined for power distribution networks (PDN), which PCB designers follow, in conjunction with tighter decoupling schemes. Board real estate limitations, application-dependent restrictions (e.g., discrete package size allowance in automotive) and cost demands further complicate the game. To address these technical challenges, engineers need to evolve from working within a disconnected design process to new or advanced design methodology with power-integrity and the demands of the PDN in mind. Using such a methodology and smart mechanisms to optimize the decoupling scheme can help ensure a design will meet the electrical specifications for power. In this two-hour workshop, the requirements and basics of PCB power distribution systems are explained in detail. The whole problem area, ranging from DC (with aspects like IR-drop, DC voltages and current distributions) to AC with its phenomena (e.g., target impedance, decoupling, inductance), is covered. Topics like plate capacitance, loop inductance and cavity resonance are explained in detail but without deep math. Side effects to the signal integrity and EMC behavior of board structures are discussed using illustrated practical examples. The role of capacitors, their parasitic behavior (ESL, ESR, connection inductance) and the technical decoupling evolution in recent years are a major part of the workshop. Guidelines for a first order covering and resolving power integrity issues are provided, regardless of the PCB design and ECAD process. Simulation capabilities addressing power integrity during PCB design will be explained and demonstrated by slides in a generic vendor-neutral manner as a problem-solving approach. Silicon vendor support documents (e.g. constraint and spreadsheet tools) to address power integrity are introduced and briefly discussed. Examples from various industries (e.g., automotive, industry automation, IoT) will complement the session with practical application experience.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced

12:00 p.m. – 1:00 p.m.
Lunch on the Show Floor, Sponsored by Sierra Circuits
1:30 p.m. – 3:30 p.m.
16: Novel Power Distribution System Design
Speaker: Dan Beeker, NXP Semiconductor

This presentation will present a simple EM physics and geometry-based approach to designing power distribution networks on PCBs. From input power connection to the IC die, the simple rules discussed can be used to reduce power supply noise and improve EMC. New research is presented on the impact of discrete components on radiated and conducted emissions, with an emphasis on cost analysis. This course will, after an introduction to EM field behavior, describe several effective methods for designing the spaces used to deliver power on a PCB. These methods are driven by considerations for how fast the switches are changing states and the geometry of the spaces and placement of components to properly delivery energy to prevent EMC and signal integrity issues.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced

1:30 p.m. – 5:00 p.m.
17: Circuit Grounding to Control Noise and EMI
Speaker: Rick Hartley, RHartley Enterprises

When time-varying (AC) signals travel in the transmission lines of a board, state-changing electric and magnetic fields are present. These fields, when not controlled, are the source of noise and EMI. In recent years ICs with very fast rise time outputs have made problems common, even in circuits clocked at low frequencies. Knowing all the basics of proper grounding will help contain and control fields, making noise and EMI issues virtually nonexistent. This 3.5-hour course will focus on the issues PCB designers and engineers need to know to prevent noise, EMI and grounding problems in today’s circuits. We will discuss what is meant by “grounding,” where energy travels in the board, location of high- and low-frequency currents, keys to controlling common mode EMI, cables and other unintended radiators, effects of IC style and packaging on overall grounding, impact of connector pin-out, best locations for IO connectors, divided planes and plane islands in the PCB, routing to control noise, best board stack-ups and filtering of single-ended and differential I/O lines.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience:Intermediate

1:30 p.m. – 5:00 p.m.
18: PCB Design and Assembly Process Strategy for High Density CSP, WLP, 2D and 3D Semiconductor Package Technology
Speaker: Vern Solberg, Solberg Technical Consulting

Topics covered: 1. BGA/CSP process technologies and standards; single die BGA and FBGA packaging, flip-chip and die-size package technologies, wafer level packaging (WLP), fan-out wafer-level packaging (FOWLP), JEDEC package outline standards. 2. Innovative solutions for 2D, 2.5D and 3D packaging, 2D BGA package technology, 3D multiple die and stacked package methodologies, implementing 2.5D for high-density BGA applications, silicon-based interposer structure, glass-based interposer structures, organic (laminate) based interposer structures. 3. Printed circuit board design guidelines for HDI, ball grid array (BGA), fine-pitch ball grid array (FBGA and DSBGA), flip-chip (WLP/FOWLP), 2.5D interposer structures; 4. HDI circuit and microvia design implementation, HDI circuit fabrication variations, microvia process methodology, design guidelines for HDI circuits, HDI sources and economic issues. 5. Specifying PCB base material, surface finish and coatings, organic-based material selection criteria, specifying thickness of copper foils, surface plating and coating variations, solder mask process considerations; 6. Preparation for high-volume assembly processing, surface mount assembly process overview, basic features needed for SMT assembly processing, system requirements for BGA and CSP device placement, palletizing to maximize assembly process efficiency, assembly process implementation.

Who should attend: PCB Designer/Design Engineer, System Designer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced

1:30 p.m. – 5:00 p.m.
19: Designing the Signal Return Path
Speaker: Susy Webb, Design Science

When designing a PCB, the signal routing and its return are critical to the circuit working properly. Great care is usually given to routing the signals, but often the return portion is the last thing considered, or sometimes it is forgotten altogether. This presentation will talk about the importance of designing that return path, with a discussion of the physics involved, where the energy flows, the interference caused when it is not controlled, and the planes and stackup needed. Additionally, we will discuss the best ways to contain energy fields, the spacing that helps prevent problems, and the routing and return movement from layer to layer. Throughout, we will discuss some signal routes and look at the paths that might set up the best possibility for a clean return.

Who should attend: PCB Designer/Design Engineer
Target audience: Intermediate

1:30 p.m. – 5:00 p.m.
20: The PCB Design Process from Cradle to Grave
Speaker: Daniel J. Smith, Raytheon SAS

This half-day course is an overview (past, present, and future) of the interactions of processes, people and technologies involved in the complete lifecycle of a PCB design. This course is designed to provide a solid foundation for those who are just starting out (zero to two years of experience) as a PCB designer and help the individual formulate a roadmap to build their knowledge base for both personal and career advancement as contributors to this industry. All attendees will receive an MS Excel checklist of the traditional questions that PCB designers should ask throughout the PCB design process.

Who should attend:PCB Designer/Design Engineer
Target audience: Beginner, Intermediate

1:30 p.m. – 5:00 p.m.
21: Place and Route for Dense High-Speed and RF Circuits
Speaker: Michael R. Creeden, CID+, Insulectro

This presentation will offer a complete view of place-and-route for dense high-speed and RF circuits. We will cover a wide range of topics, including next-generation materials, the rational for considering HDI for our products, and overall layout flow. We will discuss the technological challenges we face in both the schematic circuit rules capture, design layout and manufacturing process. Students will learn what it takes to satisfy solvability, high-speed concerns, and RF performance issues, while building a board that will be cost-effective as a reliable high-yield product. We will also review how our early integration with the manufacturing team during the design cycle will help us understand the specifics to build a product that is correct-by-construction and performs on revision-1. The focus will be on practical application and implementation using real-world examples.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced

3:00 p.m. – 5:00 p.m.
22: The Mystery of Bypass Capacitors
Speaker: Keven Coates, Geospace Technologies

How do you design a high-speed digital circuit with enough bypass caps in the right area to supply all the peak power demands? You can’t listen to all the expert advice because it seems they can’t even agree! This presentation covers power distribution network basics and shows three approaches with simulation results for each, and some real-world experience and advice on bypassing for high-speed circuits.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced

5:00 p.m. – 6:00 p.m.
Happy Hour on the Show Floor, sponsored by Ultra Librarian
10:00 a.m. – 2:00 p.m.
Booth Barista sponsored by Zuken
9:00 a.m. – 10:00 a.m.
F1: The Butterfly Effect in PCB Design: Optimization of High-speed Lines for an FMC Carrier Board
Speaker: Jamie Pacamarra, Analog Devices

When signals start to get affected by the physical characteristics of the PCB, things start to get a little tricky. A simple point-to-point connection won’t be enough to keep the integrity of the signal. High-speed PCB design focuses on addressing this issue by altering the physical conditions of and around the traces concerned.

This study is focused on an FPGA mezzanine card (FMC) carrier supporting the Software-Defined Radio (SDR) System-On-Module (SOM) from Analog Devices. It uses the peripheral component interconnect express (PCIE) topology that consists of both a transmitter pair and a receiver pair. These pairs send and receive signals, in this case, at rates up to 16Gb/s. For these signals to retain their integrity, a thorough high-speed PCB design must be implemented. But there are limitations that prevent easy high-speed routing for this design.

Since this FMC is the carrier board for an RF SOM and is designed for compatibility with an industry standard form factor for high pin count (HPC) FMC, there are components that are fixed and cannot be moved or rotated freely. With limited freedom to move components, there are high-speed lines that take longer routes. Longer traces create large current loop areas, increasing the chances for delays and noise. The challenge is to optimize the design’s high-speed lines while taking into consideration the mechanical restrictions, trace lengths, and stackup limitations through simulations.

To address these issues, three trials were simulated with the first one sticking to the original design, second with modified differential pair setup and stackup heights, and the third one with modified differential pair return path vias from inline to rectangular and implementation of vias in pads. Insertion loss, return loss, and their eye diagrams were gathered and compared to analyze how each change in the physical characteristics of the board affects the overall signal quality of the lines concerned. Insertion loss improved by -13dB, return loss by -21dB, and the eye diagram widening up to almost twice the size from the original. Note a small change in the design’s copper features contributed greatly to achieve the performance required from this application. With these results, it can be concluded that it doesn’t take rocket science to handle high-speed signals. With small changes and proper execution, PCB designers will be able to deliver a quality design, all while considering overall cost and board manufacturability.

Who should attend: PCB Designer/Design Engineer
Target audience: Beginner, Intermediate
9:00 a.m. – 10:00 a.m.
F2: Millimeter-Wave Concepts Can be Used to Optimize the Performance of High-Speed Digital Circuits
Speaker: John Coonrod, Rogers Corp.

Understanding millimeter-wave (mmWave) concepts can benefit RF designers, high-speed digital circuit designers and fabricators. In the RF industry, as frequency increases many circuit properties become increasingly difficult to control. Circuits used at mmWave frequencies (above 30GHz) have smaller wavelengths. Due to this small wavelength, circuit performance can be affected by very small circuit anomalies that in the past could have been ignored at lower frequencies. These small circuit anomalies can be caused by a variety of issues, such as normal variations of several processes for PCB fabrication, circuit designs being sensitive to the anomalies and normal variation of certain high-frequency material properties.

This presentation will give a basic overview of what to consider in order to optimize the circuit performance at mmWave frequencies. For high-speed digital circuits, the presentation will include information on how mmWave concepts can be used to optimize high-speed digital circuits as the Nyquist frequencies approach the RF mmWave frequencies.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate
10:00 a.m. – 11:00 a.m.
F3: Electromagnetic Fields for Normal Folks: Show Me the Pictures and Hold the Equations, Please!
Speaker: Daniel Beeker, NXP Semiconductor

The material presented will be focused on the physics of electromagnetic energy basic principles, presented in easy to understand language with plenty of diagrams. Attendees will discover how understanding the behavior of EM fields can help to design PCBs that will be more robust and have better EMC performance. This is not rocket science, but an easy to understand application of PCB geometry. It’s all about the space!

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced
 
 
11:00 a.m. – 12:00 p.m.
KEYNOTE: Augmented Reality New Device Challenges and Enabling Industry 4.0
Speaker: Brian Toleno, Ph.D., Microsoft

Within the electronics industry we have seen the drivers of technology move from military and industrial electronics to mobile devices. Looking to the future, a few areas are discussed with respect to rapid growth in the electronics area: internet of things (IoT), wearable devices, and AR/VR. As the number of devices sold rise to the hundreds of millions, these devices pose some unique challenges with respect to not only the optical requirements, but the electronics to drive these systems. In this presentation we will review the current devices and players in the market, explore the current technology employed to build these devices, and discuss the challenges to enable future technologies in this exciting area.

Who should attend:
Target audience:
1:30 p.m. – 2:30 p.m.
F5: Design and Implementation of Copper Coin Application Over Thermal VIA (Vertical Interconnect Access) Structure for Thermal Management up to 12W Device Application
Speakers: Marcus Miguel V. Vicedo, Analog Devices, and Richard Legaspino, Analog Devices

PCB design is the realization of an electronic circuit that encapsulates all the performance the application requires. In high-power applications, an external component is needed to dissipate heat out in the form of heatsink enhancements. The PCB, on the other hand, absorbs the thermal shock and fans it out on all the conductive layers, resulting in unscaled effect of heat on signal performance.

Copper Coin is an offered thermal solution to direct heat toward the sink mechanism. A PCB’s thermal capability according to Andonova, et al can be considered one-dimensional, as the heat is only propagating depending on the type of dielectric material used. This is expected to be lower than that of conductive material due to its dielectric behavior.

Thermally inclined designs are generally made with the use of Cu-filled VIAs to act as funnels, but the dimension of the VIA-barrel limits the propagation of heat toward the sinking mechanism. Thus, Copper Coin or embedded copper heatsink technology arose, and the PCB design becomes a vital stage in implementing this solution.

This research is about the design and development of a T-type Copper Coin to direct heat out of a 12W device application. This device requires the heat to be dissipated in as little time as possible to not affect signal performance of the PCB design. The designed structure was subjected to thermal simulations using Finite Model Simulation Tools known to be proprietary of Analog Devices. Also, a comparison of performance was made with the standard Thermal VIA structure to assess the advantages and disadvantages of using the copper coin structure in the aspect of heat dissipation. To ensure the manufacturability, the design followed manufacturing parameters from a fabricator and dwells with the basic geometry to avoid over-constraining the design.

T-Coin setup was designed to overcome the thermal VIA in terms of handling an extreme amount of heat. The design intent was to dissipate the heat toward the heatsink in the minimum amount of time. Also, the mechanical aspect of having the mechanical stiffener heatsink underneath solves the lingering setup problem during automated testing.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner
1:30 p.m. – 2:30 p.m.
F6: Accelerate PCB Platforms Layout Design Using AI Smart Router
Speakers: Naveid Rahmatullah, Intel, and Xiao Ming Gao, Intel

Traditionally, for large-complexity PCB layout, such as high-density interconnect (HDI) type designs, most of the routings are done manually. This is, in part, due to irregular routing patterns and stringent signal integrity (SI) and power integrity (PI) constraints. For simpler PCBs, the legacy auto-router can be used to improve routing speed. However, the former method has to rely on layout engineers’ experience and trial and error; routing strategies have to be evaluated one by one manually. The latter needs router control scripts debugging. Both approaches are time-consuming.

To speed efficiency and reduce time-to-market, we developed a new Artificial Intelligent (AI)-based smart router using machine learning to accelerate PCB platform layout and routing. Each routing solution, such as routing layers and via locations, are encoded into chromosomes, which are fed into a genetic optimization engine that concurrently searches through multiple design options to meet routing constraints. Then a deep learning neural net is used as the fitness function. This neural net is trained by analyzing the features of previous successful design patterns using hard-coded heuristics, such as crossovers, length, and congestion. After that, the trained neural network is used to rank the performance of each new routing strategy in parallel. This can be done using multi-core CPU and cluster-based computing resources to evaluate multiple routing strategies at the same time. We have used the AI smart router to accelerate a variety of PCB designs from special CPU interposer, power interposer to general open source PCBs, such as Raspberry Pi and Arduino boards, with great success. For example, the CPU interposer is a special kind of PCB used to enable previous generation silicon to be installed on current generation system for validations before new silicon arrival. This facilitates platform checkout and deployment, enabling early shift left platform strategy, such as firmware, BIOS, and test and validation collateral developments. The routing time is reduced from three weeks of using manual routing to under one hour using the new AI router. The power interposer is analog-centric and used to profile silicon key power rail voltage and current, and the AI router can also achieve 100% completion rate in a very short time. The AI router works with a PI analysis tool to evaluate power rail shape changes on the PI performance to guarantee the design specification is met when routing changes are necessary. The router is web-based, so users can upload a board design database to the cloud. Once the routing is complete, users will be notified. Another benefit of the AI router is that it can greatly reduce design time, including pre-layout feasibility study, board stackup definition, and component placement. The course will provide a walk-through of the routing process using AI router.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced
2:30 p.m. – 3:30 p.m.
F7: Hair-Raising Footprint Horror Stories – and How to Avoid Them
Speaker: Elizabeth Bustamante, SnapEDA

When creating libraries, standards are crucial for maintaining consistency, accuracy, and reliability. Yet, even with rigid standards in place, mistakes inevitably creep into such a detail-oriented process. In this talk, we’ll explore some hair-raising footprint horror stories and how to avoid fatal footprint mistakes on your next PCB design. Delving far beyond the basics, we’ll look at the more gnarly errors that trip up engineers. For example, we all know to double-check our pin mappings, but what about how you have interpreted the component’s orientation in the datasheet? Misinterpreting a component’s top view for its bottom view is one of the top causes of bad boards that we see.

Drawn from our community of 200,000 engineers, our hope is these lessons will prevent costly prototype iterations and delays on your next project. Finally, we’ll explore how to prevent these errors on your next designs. For example, by bringing in more verification into your processes through checklists or by creating an automated system for assessing the quality of your PCB footprints.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced
2:30 p.m. – 3:30 p.m.
F8: The Current State of Fabrication and Assembly – Dispelling Myths, Correcting Misunderstandings, and Explaining Mysteries
Speakers: Shane Shuffield, Advanced Assembly, and Mark Hughes, Advanced Assembly

Engineering is full of “rules-of-thumb” and “best-practices” based on false and outdated assumptions. Engineers need to know the current state of manufacturing technology to avoid unnecessarily constraining their design or basing their ERC and DRC on fictional rules.

This presentation will cover the current state of printed circuit board manufacturing and assembly technology, with an emphasis on correcting outdated rules and restrictions that have been made obsolete by advances in machines, materials, and process control. Participants will gain insight into how certain design decisions can affect the cost and lead-time for their projects.

Who should attend:PCB Designer/Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate
3:30 p.m. – 4:30 p.m.
F9: PSIJ Effect on SI Analysis of LP4x 4267 Mbps Speed in HHHL PCIe Card
Speakers: Ashish Gupta, Intel and Vinay Kumar Naik, Intel

A system-level SI-PI co-simulation of LPDDR4x 4267 Mbps is presented. System analysis includes 1.6mm 14L PCB, 0.8mm 10L SoC flip-chip package with memory down configuration. The board stackup is 14 layers, 4-6-4 driven by high-density memory (4 – x64 slices) and HHHL (Half Height Half Length) form factor. The LP4x memory data bytes are routed in the upper half of the stackup with microvias on stripline layers to the crosstalk with zero via stub. The command, address and control signals are half-buried to ensure safe guidelines. The low Dk (<4) and Df (<0.1) material was chosen to minimize transmission and dielectric loss, respectively. Reverse-treated foil (RTF) is used, which offers significant improvement in loss characteristics at high-speed data transfer. The FCBGA package contains approximately ~10K bums and ~2K BGA pads with 4-2-4 stackup. Die form-factor is 14 x 16mm2, to keep the package form factor as low as 25 x 25mm2, and the number of layers are optimized at 10. Elaborating more on LPDDR4x analysis, PWL currents specific to each IO power supply bump are estimated based on worst-case switching activity. These PWL currents are then fed to the power supply bumps and IO noise is generated based on PDN in package and board. On-die decaps in the range of 6nF and package/board discrete decaps of values 0.1[U]F, 1[U]F and 10[U]F are used to keep target impedance in the acceptable range. Jitter is estimated from worst-case peak to peak noise, which is called power supply-induced jitter (PSIJ). Deriving PSIJ separately for slow, typical and fast corners would reduce the pessimism involved in using the worst-case PSIJ for all the corners. After getting power supply-induced jitter, signal integrity simulation on the complete system chip+package+board is performed to evaluate write and read margins against the JEDEC eye mask. All the LPDDR4x routing in the package and PCB is done as stripline single-ended 40[O] geometry and 70[O] for DDR differentials (CLK and DQS) and maintained 2x spacing to have less crosstalks among the different DQ bits. NEXT and FEXT among DQ bits have been optimized to achieve a best return path scenario. To optimize return path, signal to ground ratio of the bump is kept at 2:1, and the ball has 1:1. Placing the ground ball ring at the PCB helps to improve return path and hence crosstalk. Locating DQS toward the center of the DQ byte group helps reduce DQ-to-DQ crosstalk. Ground via near the signal via improves the return path, and this guideline has been followed throughout the design. SI-PI co-simulation is performed by including the PSIJ into system write and read test benches. This approach eliminates any repetition of PDN consideration in SI-PI simulation. Worst-case single rank write and read margins were predicted with statistical simulation based on response surface methodology. The factors considered during simulations are PVT corners, impedance variation in package and PCB, SoC driver strength and ODT strength variation. Write and read eye diagram (including JEDEC eye mask) will be presented to affirm the claim.

Who should attend: PCB Designer/Design Engineer, System Designer, SI Engineer
Target audience: Intermediate, Advanced
3:30 p.m. – 4:30 p.m.
F10: PCB Design as an Optimization Problem
Speakers: Zachariah Peterson, Northwest Engineering Solutions

Causal transmission line design has been a critical aspect of behavior since the 100Gb/s Ethernet PHY guidelines were proposed by the IEEE P802.3bj Task Force.Causal effects in real transmission lines, as well as dispersion and losses in the system, cause deviations from target impedance, motivating a design technique that considers design to a target impedance throughout the relevant signal bandwidth.

This talk presents the use of differential evolution for optimizing causal transmission line geometries to meet a target impedance while considering the entire bandwidth of an analog or digital signal (up to 20GHz). The transmission lines shown consider skin effect, causal relationships between dielectric function and losses, and copper roughness. The results show dielectric function at a single frequency is not always an appropriate approximation for calculating signal behavior on a transmission line. Example results for microstrips, striplines and coplanar waveguides will be presented. Differential evolution will be used to show tradeoffs between crosstalk strength and conformance to target impedance.This is done by taking multiple design goals as objective functions in an optimization problems and designing the transmission line directly. This eliminates the need to take measurements of proposed interconnect designs and infer the required geometry from a regression technique. Results for single-ended and differential lines will be presented. These results provide designers a view of the tradeoffs involved in geometry and spacing optimization. These optimization techniques have never been used to directly address transmission line geometry within a defined bandwidth while considering the causal relations for the dielectric function of PCB substrates (e.g., Kramers-Kronig relations). These new techniques enable calculation of critical signal metrics in transmission lines, such asinsertion loss, return loss, S-parameters, and crosstalk strength.

Who should attend:PCB Designer/Design Engineer
Target audience: Advanced
5:00 p.m. – 6:00 p.m.
Happy Hour on the Show Floor, sponsored by Ultra Librarian

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10:00 a.m. – 6:00 p.m.
23: PCB Stackup Design and Materials Selection
Speaker: Bill Hargin, Z-zero

The objective of this tutorial is to guide design teams through the process of evaluating and selecting the right laminate for a design, creating PCB stackups that meet the requirements of complex, multilayer boards that work right the first time, within budget, and with reproducible results across multiple fabricators. The course will go into detail on tradeoffs between loss and cost, including dielectric loss, resistive loss, surface roughness, as well as glass-weave skew. After attending this course, students will be knowledgeable of PCB laminate tradeoffs, the laminate-materials market, and the process of troubleshooting problematic stackup designs. Attendees will also be exposed to cost-effective strategies for controlling loss and glass-weave skew.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate

10:00 a.m. – 12:00 p.m.
24: Mechanical Design to Control EMI
Speaker: Rick Hartley, RHartley Enterprises

As most engineers and designers are aware, EMI occurs because some mechanical structure, within or attached to our system, is capable of resonating and radiating electromagnetic field energy. Those mechanical structures can be a cable attached to the housing around our circuit boards, a part of the metal chassis, a slot in the chassis or a portion of one of the circuit boards in the system. Knowing how to control these structures so they are not capable of supporting resonance and radiation is the key to success.

This two-hour course will discuss basic physics of energy movement, metal vs. plastic enclosures, slots and openings in enclosures, shielding enclosures, shielding of components, proper shielding of cables, basic component placement for MEs, extreme importance of I/O connector placement, routing of external cables, position of cables inside the system, multiple boards in the system — best arrangement, using chassis as a heatsink, other items MEs and PCB designers need to know about PCBs and the system.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate

10:00 a.m. – 12:00 p.m.
25: Design-for-Manufacture and Design-for-Assembly Fundamentals that Decrease Holds and Lower the Cost of Manufacturing
Speakers: Mark J. Hughes, Royal Circuit Solutions and Elijah Gracia, Royal Circuit Solutions

Engineers are often only peripherally aware of the PCB fabrication and assembly process, and often make design decisions that increase cost and turn-time or decrease reliability. This presentation provides a manufacturer’s perspective of design decisions that result in holds and cost increases using examples from the past 15 years in the industry. By gaining a better understanding of how manufacture and assembly processes work, engineers will be able to design printed circuit boards that cost less and have greater longevity than their current designs.

This presentation will be split into two parts: First, we will briefly cover all phases of the manufacturing process as we follow a board from digital submission to customer delivery. Second, we will look at multiple examples of actual customer submissions and analyze them for design decisions that result in unnecessary cost increases or unnecessary holds. The presentation will conclude with a 15-minute question and answer session that allows engineers to ask questions about their designs.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience:Beginner, Intermediate

10:00 a.m. – 12:00 p.m.
26: How to Fight Magnetic Noise Gremlins
Speaker: Keven Coates, Geospace Technologies

Have you ever had a noise-sensitive circuit and tried to find the noise source? Even after you completely encased sensitive portions in all sorts of shielding, you still had noise? It’s very possible this is magnetic noise. Lower frequency magnetic fields can’t be contained and shielded against in the same way electric fields can. In this presentation, hear about the author’s nine-month long battle with a specific magnetic noise issue, the best tools to fight it, twisted pair, current loops, and the best ways to test for and defeat magnetic noise in your designs. New this year is more on how electric fields compare and some general shielding examples.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner, Intermediate, Advanced

10:00 a.m. – 12:00 p.m.
27: PCB Design Techniques to Improve ESD Robustness
Speaker: Daniel Beeker, NXP Semiconductor

Raise the shields, Scotty! Starting with some simple definitions for ESD/EOS, this session describes the important differences in the energy involved and the type of damage that can result. The presentation focuses on PCB design techniques as a means of improving system robustness.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced

10:00 a.m. – 2:30 p.m.
28: Fundamentals of Geometric Dimensioning and Tolerancing (GD&T) for the PWB Design Engineer
Speaker: Gary Ferrari

Millions of dollars’ worth of PWBs are scrapped each year due to tolerance errors in the final product. A good majority of these errors are due to incorrect tolerancing of holes, edges and other board features. This seminar will explain how GD&T can help you avoid high scrap rates and reduce overall cost due to improper dimensional tolerances. It will show how to apply GD&T to printed wiring boards without all the confusion found in complex mechanical objects such as gear trains and castings. The principles discussed follow the ASME Y14.5 standard, as well as IPC-2615, Printed Board Dimensions and Tolerances. Attendees will learn GD&T principles for printed wiring boards, appropriate symbology for drawings, and bilateral vs. geometric dimensioning.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate

12:00 p.m. – 1:00 p.m.
Lunch-n-Learn Sponsored by Polar Instruments
1:00 p.m. – 3:00 p.m.
29: Feeding the Beast: Consumption-Based PCB Design
Speaker: Daniel Beeker, NXP Semiconductor

A step-by-step guideline for determining the PCB design requirements based on device energy consumption requirements. Wave cycle times and transmission line capacity form the basis of this philosophy. The course will center on the LS1043 Network processor, with a focus on the core power supply requirements (7 A/[U]S). The session will begin with a review of EM field behavior and transmission line design, then will outline a process for analyzing the real power delivery challenge posed by a high-performance microprocessor. Starting with the DC current specification, we will use the device package pinout to determine the necessary PCB networks required to support the delivery of power to the device. The package pinout and clock frequency will be used to determine the real “coulombs per wave cycle” that the PDN must support. This will then be used to design both local storage requirements and connecting structures. A spreadsheet will be presented for performing quantitative analyses of the transmission line capability based on the impedance and length, determining the number of wave cycles needed to deliver the required charge. This perspective can be used in the initial design phase or to evaluate existing designs. EMC test results from a production design, MPC-LS-VNP-MOD, using this approach, will be presented.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced

1:00 p.m. – 4:30 p.m.
30: PC Board Design of Power Distribution and Decoupling
Speaker: Rick Hartley, RHartley Enterprises

Power distribution in PCBs is the foundation around which all things work in the circuit. If this is not designed correctly, the entire circuit is at risk from noise and signal integrity issues, to say nothing of the severely increased possibilities of EMI. Low impedance in the structure, across the harmonic frequency range of a digital circuit is critical. A number of subtle layout techniques will have major impact on power bus impedance, inductance in particular. This 3.5-hour course will cover power bus target impedance, inductance of vias, planes and capacitors, mounting inductance of capacitors, energy delivery to IC cores, the “Bandini Mountain,” best mounting of capacitors based on board stack-up, the importance of IC pinout, placement of decoupling in both low-layer-count and high-layer-count boards, real performance of capacitors (vs. myth), how much decoupling, multiple capacitor values, how to minimize anti-resonant peaks, ferrites in the power bus, analog and RF decoupling, the importance of power/ground plane pairs, ultra-thin power and ground plane pairs and the importance of board stack.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Intermediate, Advanced

1:00 p.m. – 4:30 p.m.
31: The Basics of PCB Fabrication (101)
Speaker: Paul Cooke, AGC Nelco – Taconic

With ever-decreasing geometries and increased density, today’s PCBs are extremely complex. Fabricators are continually under pressure to keep up with the capabilities needed to produce these types of products. This seminar looks at how a PCB is fabricated and the challenges the fabricator faces to achieve the design intent and meet customer and industry standards. We will examine the processes needed to form microvias, image [U]BGAs, plate copper in holes the thickness of a human hair and select surface finishes needed for very tight pitch components. The half-day seminar will be interactive with the audience to ensure all questions related to more in-depth PCB fabrication and processes are answered.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, Fabricator Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate

1:00 p.m. – 4:30 p.m.
32: Routing Digital Boards to Avoid Problems
Speaker:Susy Webb, Design Science

There are many ways to route a PCB, some much more effective for signals than others. The first design rule is that the board must work properly, so it is important to have a plan that addresses good signal quality and crosstalk control, no matter what the frequency. In this presentation, we will start with a bit of the science to set up the reasoning for routing a certain way, then move into return current and impedance control, with a discussion of what affects those things. Starting route with an effective fanout plan sets up what is to come, and we will also explore general routing priorities and concerns. To avoid problems, routing schemes will be addressed, along with spacing, differential pair and length matched routing. Last, pros and cons of hand routing, semiautomation, and autorouting will be examined.

Who should attend: PCB Designer/Design Engineer
Target audience: Intermediate

1:00 p.m. – 4:30 p.m.
33: Heterogeneous OR Mixed-Up Assembly
Speaker:Phil Marcoux, PPM Associates

In recent years heterogeneous assembly has grown in interest as a possible replacement for SMT assembly and as a solution for reducing the area needed for complex electronic devices. Heterogeneous devices combine packed devices, unpackaged devices, bare chips, chiplets, deposits, components and intricate substrate materials and designs. In some cases heterogeneous devices are more economical and offer faster time to market and lower product costs than custom and semi-custom integrated circuits.

The successful design, procurement, and manufacturing of a heterogeneous product is exacting, requiring the interaction of multiple vendors, marginally adequate design and testing tools, and often reluctant component vendors. For those designers and product managers willing to understand and endure the road to product completion, the rewards can be great. Missteps can be career-limiting.

This seminar will cover the basic and advanced assembly options, component variations, and common substrate types. It will review the latest changes to the Heterogeneous Integration Roadmap (HIR) developed by the multi-standards organizations.

Who should attend: PCB Designer/Design Engineer, System Designer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate

10:00 a.m. – 4:00 p.m.
34: Power Delivery System Design
Lee Ritchey, Speeding Edge

With the advent of ICs with multiple power rails at very high currents, the design of the power delivery system in a modern product is often more difficult than routing the PCB to ensure good signal integrity. The power delivery system must deliver power to devices at frequencies from D to hundreds of megahertz. The application notes that accompany most ICs do not contain adequate information to allow a designer to get the PDS correctly designed.

This course is aimed at providing the information needed to get the job done right. It draws on the speaker’s experience designing hundreds of power delivery systems for products ranging from satellites to super computers. It contains a very large number of test PCBs used to determine how well each component will perform when used in a PDS.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced

10:00 a.m. – 6:00 p.m.
35: PCB Problem Solving – PCB 102
Speaker: Paul Cooke, AGC-Nelco Taconic

This course will address advanced problem solving of printed wiring board defects. Some defects, such as interconnect separation, delamination, wedge voids, plating folds, micro-voids, surface pitting, and hole wall pull-away, carry significant costs. Many are difficult to solve because the root cause may not be readily apparent, and multiple factors may contribute. This course will explore the most intricate of these factors and how the interrelationship of up- and downstream processes contribute to scrap product. What effect does drilling have on hole wall quality and the subsequent metallization process? Participants will learn how to recognize problems like this and take corrective action. The course will explore a myriad of electrodeposition defects, such as mouse bites, pitting, and domed or crown plating. Solderability and assembly-related issues such as outgassing, black pad, creep corrosion and blow holes will also be discussed. The course will conclude with a discussion on imaging, including liquid-photoimageable solder masks. Strategies to solve solder mask peeling, poor circuit trace coverage, skips, bubbles, and poor adhesion in nickel gold plating will be discussed. Solder mask equipment and its effect on solder mask quality will also be explored. In addition, over 200 images of defects will be presented.

Attendees will learn how to recognize and solve lamination and other multilayer-related defects; electrodeposition defects: mouse bites, pitting, nodules, crown or dome plating, dog bone defects; copper plating reliability; how to improve plating distribution and throwing power; metallization: microvoids/voiding, interconnect separation, hole wall pull away, and assembly issues; black pad phenomenon: new details on its cause and how to eliminate it; imaging: defects, surface preparation, solder mask issues and defects, process control. Also covered will be other final finish-related defects: creep corrosion, champagne bubble effect, solder mask interfacial attack. Participants should have some knowledge of the PCB fabrication process. This course will directly benefit those involved in printed circuit board fabrication and assembly. In addition, PCB end-users and designers will gain significant knowledge about PCB-related defects.

Who should attend: PCB Designer/Design Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Intermediate, Advanced

1:00 p.m. – 4:30 p.m.
36: Flexible and Rigid Flex Circuits: Design, Fabrication and Assembly Process Principles
Speaker: Vern Solberg, Solberg Technical Consulting

Flex circuits typically replace the common hard-wire interface between electronic assemblies. Flexible circuits, however, have significant advantages over the hard-wired alternative because they fit only one way, eliminate wire routing errors, and save up to 75% on space and weight. The design guidelines for flexible circuits, although similar to rigid circuits, are somewhat unique. In essence, flex circuits furnish unlimited freedom of packaging geometry, while retaining the precision density and repeatability of printed circuits. Because the flex-circuit conductor patterns can maintain uniform electrical characteristics, they contribute to controlling noise, crosstalk, and impedance. Flex circuits will often be designed to replace complex wire harness assemblies and connectors to further improve product reliability. During the half-day tutorial program, participants will have an opportunity to review and discuss the latest revision of IPC-2222 and IPC-2223, “Sectional Design Standard for Flexible Printed Boards,” that includes base material sets, alternative fabrication methodologies and SMT-on-flex assembly processes. The workshop will also furnish practical flex circuit supplier DfM recommendations for ensuring quality, reliability and manufacturing efficiency. Topics of discussion: 1. Applications and use environment (commercial/consumer, industrial/automotive, medical/aerospace); establishing end-use criteria 2. Designing flexible and rigid-flex circuits (flex circuit outline planning; circuit routing and interconnect methodologies; fold and bend requirements; SMT land pattern reinforcement criteria). 3. Material and SMT components (IPC standards for flex and rigid-flex dielectrics; base material and metallization technologies; selection criteria for SMT components; SMT land pattern development). 4. Assembly processing of flex and rigid-flex circuits (dimensioning and tolerance criteria; palletized layout for inline assembly processing; SMT assembly process variations and methodologies, alternative joining methods for flexible circuits).

Who should attend: PCB Designer/Design Engineer, System Designer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate