10:00 a.m. to 12:00 p.m.
1 .  AC/DC? DC to AC? Power Integrity and Decoupling Primer for PCB Designers – A Practical Introduction
Speaker: Ralf Bruening , Zuken

Electronic systems are changing our way of life, many of them utilizing complex ICs and various functionalities which increase in capabilities on a daily basis. The power demand in both power consumption and quality of the power supply grows significantly in concert with these changes. In parallel, IC supply voltages tend to decrease with every new silicon generation, contributing to the goal of reducing the overall power consumption of the systems. This defines (in conjunction with the shrinking noise margins) increasing demands for the stability of the power distribution in these multilayer PCBs.

As a consequence, tighter rules and constraints from silicon vendors are specified for the so-called power distribution networks (PDN) and the decoupling which PCB designers must follow. Board real estate limitations (IoT designers fight for every square mil), application-dependent manufacturing restrictions (e.g., discrete package limitations such as those in automotive) and cost targets add fuel to the fire.

To mitigate such design challenges, engineers need to evolve from working based on rules-of-thumb within a disconnected fragmented design process to new or advanced design methodology with power-integrity and the electrical demands of the PDN in mind. Using such a methodology and smart tooling to optimize, for example, the decoupling scheme, can help to ensure that a design will meet the electrical specifications for power. In this two-hour workshop, the basics of PCB power distribution systems with their various requirements are explained in detail. The whole problem space, ranging from DC (with aspects like IR-drop, DC voltages and current distributions) to AC with its different phenomena (e.g., noise voltage, target impedance, decoupling, inductance) is covered.

Topics like plate capacitance, loop inductance and cavity resonance are explained in detail but without deep math. Side effects to the signal integrity and EMC behavior of board structures are discussed using illustrated practical examples. The role of decoupling capacitors, their parasitic behavior (ESL, ESR, connection inductance) and the technical evolution in recent years are another major part of the workshop.

Guidelines for practical addressing and resolving power integrity issues are provided, regardless of the PCB design and ECAD process attendees use. Simulation capabilities addressing power integrity during PCB design will be explained/shown in a generic vendor-neutral manner as an industry-proven problem-solving approach. Silicon vendor support documents (e.g., constraint and spreadsheet tools) to address power integrity are discussed. Examples from various industries (e.g., automotive, industry automation, IoT) and an outlook where PI support will head to with the emerging of A/ML into engineering will complement the session.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Test Engineer
Target audience:  Beginner, Intermediate, Advanced
10:00 a.m. to 2:30 p.m.
2 .  Boot Camp – Science-Based Power Supply Design, Part 1
Speaker: Dan Beeker , NXP Semiconductor

This is a six-part class taught over two days.

Part 1: Electromagnetic Fields for Normal Folks: Show me the pictures and hold the equations, please! This section focuses on the physics of electromagnetic energy basic principles, presented in easy-to-understand language with plenty of diagrams. Attendees will discover how understanding EM field behavior can help design PCBs that will be more robust and have better EMC performance. This is not rocket science, but an easy-to-understand application of PCB geometry.

Part 2: Effective PCB Design: Techniques to Improve Performance. As IC geometries continue to shrink and switching speeds increase, designing electromagnetic systems and printed circuit boards to meet the required signal integrity and EMC specifications has become even more challenging. A new design methodology is required. Specifically, the utilization of an electromagnetic physics-based design methodology to control the field energy in your design will be discussed. This module reviews the development process and provide guidelines for building successful, cost-effective printed circuit boards.
After introducing EM field behavior, this segment describes several effective methods for designing the spaces used to direct EM fields on a PCB. Simple rules for managing these fields will be described, based on one fundamental behavior. How fast does the switch change states? This defines the requirements for the power distribution and the geometry of the space between the output of the switch and the receiver. Several real-world examples of the use of these principles, both for designing compliant boards and for analyzing EMC failures are presented.

Part 3: Novel Power Distribution System Design. This section presents a simple EM physics and geometry-based approach to designing power distribution networks on PCBs. The simple rules discussed can be used to reduce power supply noise and improve EMC from the input power connection to the IC die. New research will be presented on the impact of discrete components on radiated and conducted emissions, with an emphasis on cost analysis.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Test Engineer
Target audience:  Beginner, Intermediate, Advanced
10:00 a.m. to 2:30 p.m.
3 .  Part Placement Choices and Consequences
Speaker: Susy Webb , DesignScience

There are many ways to place parts on any board, but clearly some work much better for the physics, electrical, mechanical and manufacturable purposes. If a new board connects electrically but is noisy, won’t work properly with the potential stackup or routing, or won’t interface properly with the rest of its system, it may require costly, time consuming redesign and retesting. That could mean a poor time-to-market for the product and possible loss of revenue for the company.

Designers must understand the board – how it will need to flow and what it will need to accomplish, the electrical frequencies and needs of the parts selected, and the overall needs of the system into which it will fit. When the board engineer understands the reasoning behind these things, and the affects they have on one another, they will intuitively know how to make good decisions for their board designs and thus avoid problems.

This presentation discusses:

  • Effective parts selection
  • The reasoning for the floorplanning and order of overall placement
  • Understanding how placement can set up effective routing
  • Board and system consequences of poor choices.

Additionally, we will discuss fine-tuning placement ideas and their effect on manufacturability.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Test Engineer
Target audience:  Beginner, Intermediate
10:00 a.m. to 2:30 p.m.
4 .  Circuit Grounding to Control Noise and EMI
Speaker: Rick Hartley , RHartley Enterprises

When time-varying (AC) signals travel in the transmission lines of a board, state-changing electric and magnetic fields are present. These fields, when not controlled, are the source of noise and EMI. In recent years, ICs with very fast rise time outputs have made problems common, even in circuits clocked at low frequencies. Knowing all the basics of proper grounding will help contain and control fields, making noise and EMI issues virtually nonexistent.

This 3.5-hour course will discuss and define:

  • “Grounding” defined and energy movement in a PCB
  • Keys to controlling common mode energy and resulting EMI
  • Cables, heat sinks, board edges and other unintended radiators
  • Effects of IC style and packaging on overall grounding scheme
  • Impact of connector pin out on containment of energy
  • Divided planes and plane islands in the PCB
  • Best PCB stack-ups for optimum grounding schemes.
Who should attend:  “PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience:  Beginner, Intermediate, Advanced
10:00 a.m. to 2:30 p.m.
5 .  Signal Integrity in Thin PCB Materials and IC Substrates
Speaker: Zachariah Peterson , Northwest Engineering Solutions

HDI and UHDI designs push the limits on layer thickness in conventional materials. Thinner low-Dk materials have also enabled much higher layer counts without HDI manufacturing requirements, but the impacts on SI, PI, and EMI are not always understood. Due to the interplay between line width, allowable line spacing from an SI perspective, Dk value, and layer thickness, it is important to understand how signal behavior is altered when designs are pushed into thinner materials.

This presentation will show how thinner materials and their Dk values affect signal integrity, as well as what designers can do to hit SI targets by balancing Dk, copper roughness, and laminate thickness. These trends will be discussed in terms of HDI/UHDI PCBs, but the same trends are seen in IC substrates, and the implementation of those practices for more advanced PCBs will be discussed to illustrate how to support bandwidths up to 56GHz. Topics to be presentedinclude:

  • An explanation of the trend toward lower Dk in terms of line width/spacing densities
  • How Dk and layer thickness affect single-ended crosstalk and differential crosstalk
  • How thick low-Dk materials vs. thin moderate-Dk materials affect signal integrity
  • How routing and via structures in HDI/UHDI PCBs and packaging affect signal integrity and available channel bandwidth
  • Examples showing how Dk and layer thickness are used to enable broadband transmission in single-ended nets, RF nets, and differential nets.

Simulation examples from real designs will be presented to illustrate the design tradeoffs listed above, and implementation in real designs will be shown as examples. Designers will learn how to balance tradeoffs among Dk value, Df value, copper roughness, and laminate thickness when selecting stackup materials based on the frequency range that is important in their systems.

Who should attend:  PCB Designer/Design Engineer, SI Engineer
Target audience:  Intermediate, Advanced
10:00 a.m. to 2:30 p.m.
6 .  Design for “X”
Speaker: John Watson , Altium

With a precursor look at the fabrication and assembly process, first, look at each step in detail to see how the ECAD data relates and are used to the steps in the process by understanding how the design process impacts the fabrication and assembly processes.

We are now ready to look deeply into several Design for “X” concepts.

Design for Manufacturing (DfM). Relates to optimizing the design to enhance the ease and efficiency of the manufacturing process. It involves considerations that facilitate cost-effective production and minimize the likelihood of errors during manufacturing. Key DfM principles include proper component placement, rationalized layer stack-ups, and adherence to industry-standard design rules. Minimizing complex geometries and using standard component footprints contributes to manufacturability. Additionally, DfM considers the capabilities of the chosen fabrication and assembly processes, ensuring alignment with industry standards to streamline production. Manufacturers can reduce lead times, enhance yield rates, and improve overall product quality by prioritizing DfM in PCB design.

Design for Test (DfT). Cover the features that facilitate efficient and effective testing of electronic circuits. DFT aims to simplify the testing process, reduce testing time, and enhance fault detection. Techniques include incorporating test points, boundary scans, and built-in self-test (BIST) features. Test points allow easy access for manual or automated testing, while boundary scan enables testing of interconnected devices. BIST involves embedding test circuitry within the design to check functionality autonomously. By integrating DfT strategies, PCB designers improve the design testability, enabling faster and more accurate identification and resolution of potential issues during the manufacturing and testing phases.

Design for Reliability (DfR). PCB design involves creating robust and durable electronic systems that meet or exceed specified performance levels throughout their intended lifespan. DFR strategies focus on minimizing the likelihood of component failures and ensuring the product withstands environmental stressors. This includes selecting high-quality components, implementing effective thermal management, and considering factors like vibration, humidity, and temperature extremes. Redundancy, proper derating of components, and thorough testing during the design phase contribute to enhanced reliability. By incorporating DfR principles, PCB designers aim to create products with improved long-term performance, reduced maintenance requirements, and increased customer satisfaction.

Design for Maintenance (DfM). This involves creating electronic systems that are easy to troubleshoot, repair, and maintain throughout their lifecycle. DfM strategies focus on simplifying access to components, minimizing the need for specialized tools, and providing clear documentation. Modular designs and well-organized layouts facilitate component replacement and upgrades. Standardized connectors and clearly labeled interfaces streamline maintenance tasks. Additionally, incorporating diagnostic features and self-test capabilities aids in identifying and isolating issues efficiently. By prioritizing DfM, PCB designers contribute to reduced downtime, faster maintenance procedures, and cost-effectiveness in managing and sustaining electronic systems over time.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience:  Beginner, Intermediate
12:00 p.m. to 1:00 p.m
Lunch-N-Learn (Tuesday Conference Attendees Only)
Speaker: Sponsored by Polar Instruments


1:30 p.m. to 2:30 p.m.
7 .  PCB DfM (A Comedy Routine Depicting a Typical Dialog between a PCB Designer and Fabricator)
Speaker: Stephen Chavez, Siemens, and Gerry Partida, Summit Interconnect ,

PCB designers just don’t simply connect the dots or push the magic button, as some may suggest. They design complex PCBs that contain physical packages smaller than ever before while addressing electrical, mechanical, and thermal variables and cost. Success in PCB design means knowing and understanding what you are doing and how the decisions made and implemented upstream have downstream ramifications.

There are key factors in achieving success in PCB design. In this presentation, the speakers focus on the relationship between design and fabrication. We’ discuss industry best practices within the design to fabrication process, along with the pros and cons that affect ROI when best practice recipes are implemented and when they are not implemented (the cost of doing nothing).

With today’s EDA tools, and eagerness of suppliers offering their technical support, the potential for success is higher than ever. This collaborative approach makes a positive difference in getting it right the first time, reducing respins (cost), increasing yields, and ultimately getting to market faster.

What you will learn:

  • Increase productivity and proficiency in PCB design to fab
  • Capitalize on existing industry best practices of DfM and manufacturing outputs
  • How you can reduce cost
  • A short comedy scenario depicting the dialogue between a principal PCB designer and a fabricator.
Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience:  Beginner, Intermediate, Advanced
3:00 p.m. to 4:00 p.m.
8 .  Printed Circuit Engineering Association Annual Meeting
Speaker: Chairman: Stephen Chavez , Siemens

Come learn about the Printed Circuit Engineering Association, an international network of engineers, designers, and anyone related to printed circuit development. Its mission is to promote printed circuit engineering as a profession and to encourage, facilitate, and promote the exchange of information and the integration of new design concepts through communications, seminars, workshops, and professional certification through a network of local and regional PCEA-affiliated groups.

Our annual awards for Leadership and Membership will be presented, and our board of directors for 2025-26 will be announced.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience:  Beginner, Intermediate, Advanced
4:00 p.m. to 5:00 p.m.
9 .  Harnessing the Power of AI in PCB Design: Addressing Challenges and Unlocking Opportunities
Speaker: David Wiens , Siemens

The role of artificial intelligence (AI) in PCB design has become increasingly important due to a combination of factors, including a workforce crunch, the explosion of complexity and cost, and tighter delivery schedules. This session explores the significance of AI in PCB design considering these factors, and highlights the benefits it brings to address the challenges faced by the industry.

First, the workforce crunch’s lack of engineering pipeline and experienced designers exiting the workforce pose a significant threat to the PCB design industry. Traditional design methods heavily rely on human expertise, which is becoming scarcer. AI can help mitigate this challenge by automating certain design processes, reducing the workload on designers, and augmenting their capabilities. By leveraging AI-powered tools and algorithms, designers can overcome the scarcity of talent and ensure the continuity of efficient and timely PCB development. By leveraging AI’s capabilities, designers can meet tighter delivery schedules without compromising on quality or performance.

Second, the explosion of complexity and cost in PCB design demands more advanced solutions. Modern electronic devices require intricate designs with high-density component placement, complex routing, and stringent performance requirements. AI can analyze large amounts of data and identify patterns that humans might overlook, enabling more accurate predictions and optimizations. This results in improved design quality, reduced costs, and enhanced performance, allowing designers to tackle the increasing complexity in an efficient and effective manner.

This session will address risks to deploying AI technology in a design process. It will also cover practical ways that AI can be applied to PCB design for assistive development, design optimization through deep learning, or generative processes that address highly complex problems. PCB engineering teams that want to stay ahead of the curve can adapt and embrace the opportunities at AI-infused design will deliver.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, COO/Sales/Marketing
Target audience:  Intermediate
4:00 p.m. to 5:00 p.m.
10 .  How to Protect Your IP When Working with Your Manufacturing Partners
Speaker: Ivan Aduna , Koh Young

Fears of design data security needs should not prevent you from accelerating your NPI flow and improving the quality of manufactured products. Providing detailed design data to manufacturing partners in a smart digital format is needed to facilitate advanced functionality, accelerate NPI, and improve product quality. As the technology of inspection and testing of assembled PCBs evolves, detailed design data is needed to facilitate advanced functionality, as well as reducing programming and preparation time for production.

This presentation talks through the process of how to exchange detailed smart design data between design and manufacturing partners, how it is made secure, and how design IP can be protected with enhanced data security. We illustrate the mechanism of how the design data in IPC-2581 (DPMX) format can be securely exchanged across the internet directly from design to manufacturing using encrypted IPC-CFX (Connected Factory Exchange) messages.

Once processed, design data in IPC-2581 format by digital manufacturing engineering tools, that resolve merge production BOM, create operator work-instructions and make dynamic line assignments, as well as the same IPC-2581 data is sent directly to by the production machines together, with work-instructions elevates programming performance, reduces data preparation times and eliminates mistakes ready for advanced programming by the machine vendor in the minimum time. This can be achieved without risk of unauthorized access or use of design data. We also look at the reverse information flow for DfX, using the same secure mechanism, that allows designers to understand the potential for design improvement based on actual manufacturing capabilities.

This presentation is suitable for all engineering and management levels, in design and manufacturing, who have concerns related to data and IP security, as they seek to transition toward smart manufacturing.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience:  Beginner
4:00 p.m. to 5:00 p.m.
11 .  Propagation Delay Analysis by Employing Various PCB Manufacturing Process
Speaker: Jaeho Choi , Samsung Electronics

Generally, all manufacturers make product using several vendors because of supply chain management (SCM). But there are hurdles to establish an integrated standard of the electrical characteristics for high-speed system performance demands. One of the main factors is the manufacturing environment element variations between vendors. Likewise with memory module PCBs, differences such as via process, raw material selection and processing occur, which results in signal integrity characteristic problems such as timing and impedance. Especially, the raw material process diversity of PCB vendors affects the dielectric constant and acts as a major factor in signal timing.

This presentation looks at how the difference in dielectric constant by vendors affects timing and discusses methodologies to control it. To clarify the level of effects between dielectric constant and propagation delay (tPD), four vendors produced the three-stack sequential structure 16-layer evaluation PCB, with three hole types (plated through-hole, blind via hole, through pin hole without via) of 50-ohm impedance signal and each signal having two types of 100mm and 120mm lengths. First, since we wanted to find out the timing difference and how the waveform is formed caused by dielectric constant produced differently for each vendor in the same signal group, we needed to align statistics through a calculation method that subtracts the time of a short length (L2) from the time of a long length (L1) at the same standard impedance and based on that, measured tPD at time domain using by vector network analyzer (VNA) with SMB connector.

Even if a difference exists of up to 30ps long tPD at each 120mm and 100mm length to length between vendors, the results are derived at a level that can be managed within an average of 10ps timing difference, calculated by subtracts from long length to short length, and it is predicted that the electrical characteristics management in mass production will be possible by using this. We study whether we can manage the diversity of raw materials by utilizing the level of impedance and timing specification tolerance.

Who should attend:  PCB Designer/Design Engineer, System Designer, SI Engineer, Test Engineer, Fabricator Engineer/Operator
Target audience:  Beginner
4:00 p.m. to 5:00 p.m.
12 .  Toward Optimal Surface Finishing of PCBs: Sustainable Solution for Automated and Optimized Cu Balancing and Cu Electroplating Step
Speaker: Agnieszka Franczak , Elsyca NV

PCB manufacturing relies on building a physical PCB from its design, accounting for a set of required specifications. Understanding the design specs is crucial as it has a direct impact on the PCB’s fabrication process, performance and productivity yield rate. One such spec of interest is copper balancing: copper traces distribution in every layer of the PCB stackup, which provides exceptional electrical and thermal characteristics necessary for signal transmission and heat dissipation.

If the copper distribution is uneven, mechanical misalignments such as board twists, bow or warpage can occur. Thus, one of the tasks a PCB designer performs is to balance the copper trace distribution so mechanical properties can be improved. An optimized copper balance also ensures homogenous copper plating across each PCB layer, creating uniform copper layer thickness on the plated surfaces. This in turn, improves signal transmission and overall PCB performance, provides consistent PCB thickness during lamination and reduces the risk of low-pressure surface areas that may result in redesign.

Copper electroplating plays an extremely important role in PCB manufacturing, and its major advantage is to reduce the ground line impedance and voltage drop. The process performance directly affects the quality of the copper layer and related mechanical properties: in acid copper plating, the challenge is to achieve proper thickness distribution and surface uniformity without unduly compromising metallurgical properties, such as percent elongation and tensile strength of the deposit. Reducing current density can equalize the copper thickness to some extent, but leads to an inordinate increase in the overall plating time, affecting the throughput of PCBs drastically. Therefore, the proper control of the process performance and consequently, the quality of the electroplated copper layer, are both important parts of the PCB plating technique, which remains one of the challenging processes even for relatively experienced PCB factories. Thus, it seems that an upfront recognition of the plating process performance in terms of the copper layer coverage and thickness would add a great value to the proper process design and control.

With the recent computer simulation technology development, PCB designers can now perform fully automated and optimized copper balancing activities, ensuring designs are free of redesign risks and fabricated toward required copper distribution and thickness specs. Furthermore, the copper balancing tool can be integrated within their design business logic.

This talk will highlight issues caused by poor copper balancing at the design stage, a mitigation strategy to address the issues, and the workflow of the integration process, which creates a smart design. The concept of a digital twin of the copper plating process in PCB manufacturing and the use of a computer-aided analysis approach for a quick assessment of the under- and over-plated surface areas, and their further mitigation toward required thickness tolerances will be discussed as well, as it is aligned with Industry 4.0 and smart manufacturing concepts.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test Engineer, Fabricator Engineer/Operator, CEO/COO/Sales/Marketing
Target audience:  Beginner, Intermediate, Advanced
4:00 p.m. to 5:00 p.m.
13 .  Best Practices for HDI and Sub-Lamination Structures: Overcoming Challenges for Optimal Yield and Performance
Speaker: Gerry Partida , Summit Interconnect

High-density interconnect (HDI) and sub-lamination PCBs provide enhanced functionality and compact designs. The success of these complex boards relies on following common best practices, however. Failure to do so can result in low yield, variations in the finished product, and, in extreme cases, make it impossible to build. This presentation will discuss important design best practices for HDI and sub-lamination structures.

Topics covered during this presentation include:

Unbalanced constructions. Unbalanced construction of PCBs can lead to signal integrity issues and compromise the overall performance of the boards. Achieving a balance between layers, considering factors such as impedance and heat dissipation, is crucial for optimal functionality.

Foil lamination. Inconsistencies in the lamination process can result in delamination or signal degradation, affecting board reliability. It is important to carefully select appropriate materials to ensure uniform lamination throughout the manufacturing process.

Cap core. The integration of capacitor layers within the core introduces complexities that, if not managed properly, can lead to variations in capacitance and impedance. Thorough testing and simulation are important to overcome these challenges.

Buried/blind vias. Improper placement of buried and blind vias can lead to signal crosstalk, impedance mismatches, and other signal integrity issues. Designers must carefully consider the placement and routing of these vias to maintain the integrity of the signal path.

Microvias. Microvias add an additional layer of complexity to PCBs. Ensuring the reliable formation of microvias without compromising structural integrity requires advanced manufacturing techniques and rigorous quality control.

Simplified processes. Streamlining the manufacturing process by reducing the number of steps can improve yields. Finding the right balance between process simplification and maintaining the integrity of the final product is essential.

Who should attend:  PCB Designer/Design Engineer, Fabricator Engineer/Operator
Target audience:  Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
14 .  Avoiding Assembly Pitfalls – DFA/DfM Lessons for First PCB Runs
Speaker: Keven Coates , OnwardAir

New system designs often have a 33% fail rate! Learn how to make that significantly better through parts placement, orientation, and knowledge of the assembly process. This class is less about PCBs and more about learning to work with assembly shop practices and understanding the assembly process. This class is based on the presenter’s experience as the EE in charge of working with the in-house assembly operation to increase yield. Design for assembly (DfA) is crucial to improving first runs and getting them to production-friendly yields.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, Assembly Engineer/Operator
Target audience:  Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
15 .  Differential Pair Design for 112 Gbps and Faster Systems
Speaker: Zachariah Peterson , Northwest Engineering Solutions

Differential pairs are the primary routing style used in many high-speed digital protocols. The current class of advanced digital systems will rely on data rates up to 224Gbps channels with PAM-4 modulation. Examples include data center architecture, servers, compute accelerators, and high-end applications in mil-aero. This presentation will show the fundamental theory and practical applications of designing differential interconnects for these very high data rates.

Designers will learn important contextual points surrounding differential pair design and routing in high-speed PCBs as they apply to 112G and faster systems. Some basic factors affecting signal integrity at high speeds and in high-bandwidth protocols will be presented. The resulting design decisions and best practices will be supported by simulation data prepared by the author and from other experts in the field.

Topics to be addressed and lessons learned include:

  • Examples of PCB stackups that can support routing in these systems
  • How materials affect SI at these very high data rates
  • Via designs targeting 28 and 56GHz bandwidths
  • SI factors such as mode conversion and reflections
  • Examples from demonstration/test boards that illustrate best design practices
  • Factors affecting differential channel bandwidth
  • Approaches for modeling designs targeting these bandwidths.

Examples of real systems that were designed by the author and have entered volume manufacturing will be presented to illustrate these important concepts. Simulation examples will also be used to help illustrate the importance of certain design choices, and to illustrate some basic rules that help ensure signal integrity. Designers will learn the important concepts and practices required for successful differential pair design and routing in systems operating from lower speeds up to 56GHz bandwidths.

Who should attend:  PCB Designer/Design Engineer, SI Engineer
Target audience:  Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
16 .  PCB Thermal Design: Quenching the Blaze
Speaker: Ethan Pierce, Pierce Design, and Tomas Chester , Chester Electronic Design

Amid the fast-paced advancements in PCB design, thermal consideration and thermal management of designs is of paramount concern. Engineers and designers are constantly seeking innovative ways to meet efficiency and reliability standards. This seminar aims to explain complex thermal theories and introduce practical approaches to optimizing PCB design for superior thermal performance. An examination and understanding of the design strategies and process to promote a performant and reliable system. This will be tied together with design examples and personal anecdotes.

Key topics to cover:

  • An explanation of heat transfer mechanisms: Conduction, convection and radiation, will establish a solid foundation in order to explore thermal management in PCB design
  • Introducing the process of the Thermal Design Engine and how it applies to your applications
  • Unveiling the process of preliminary thermal structuring, physical testing, and refinement of the system, illustrated through case studies.
    Further, the seminar delves into the diverse landscape of PCB materials and design strategies:
  • A comprehensive overview of IMS and aluminum boards, shedding light on material selections, stackup configurations, and the mantra “copper is your friend” in board design
  • An introduction to copper coins, their types, applications, and their important role in heat dissipation, complemented by a real-world high-power MOSFET design case study and a comparative analysis of a high-power MOSFET with and without a copper coin
  • A showcase of simulations reflecting the impact of conductive vs. nonconductive fill vias in thermal management.
    The discussion explores simulations on thermal performance with a comprehensive simulation, evaluating the thermal performance of the discussed design strategies, and integrating learned concepts into system design.

What you will learn:

  • Real-world examples and hands-on experience with various thermal management strategies
  • Techniques for effective thermal simulation, analysis, and integration into their PCB design workflow
  • Insights into collaborative frameworks that foster innovation in thermal management, de-risking designs, increasing the likelihood of success and reliability.

Join us to demystify the intricacies of thermal management in PCB design and propel yourself toward a mastery of the art and science of creating thermally efficient and reliable systems.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test, Engineer, Fabricator Engineer/Operator
Target audience:  Beginner, Intermediate
10:00 a.m. to 3:00 p.m.
17 .  Boot Camp – Science-Based Power Supply Design, Part 2
Speaker: Dan Beeker , NXP Semiconductor

The second half of a six-part presentation.

Part 4: Feeding the Beast: Consumption-based PCB Design. This session is a step-by-step guideline for determining the PCB design requirements based on device energy consumption requirements. Wave cycle times and transmission line capacity form the basis of this philosophy. The segment will begin with a review of EM field behavior and transmission line design, then outline a process for analyzing the real power delivery challenge posed by a high-performance microprocessor. Starting with the DC current specification, we will use the device package pinout to determine the necessary PCB networks required to support the delivery of power to the device. The course will center on the LS1043 Network processor, with a focus on the core power supply requirements (7A/uS). The package pinout and clock frequency will be used to determine the real “coulombs per wave cycle” the PDN must support. This will then be used to design both local storage requirements and connecting structures. A spreadsheet will be presented, which can be used to do a quantitative analysis of the transmission line capability based on the impedance and length, so the number of wave cycles needed to deliver the required charge. This perspective can be used in the initial design phase or to evaluate existing designs. EMC test results from a production design, MPC-LS-VNP-MOD, using this approach, will be presented.

Part 5: Stacking the Deck: Maximizing the PCB Layer Design for Signal Integrity and EMC Performance. This segment focuses on the importance of understanding the role of the PCB layers in directing the signal and power supply energy between the board layers. The focus is on knowing which dielectric you are using, and how to move that energy between dielectric layers in the PCB.

Part 6: HDI Via Design: Planning the Energy Pipelines. This segment focuses on the importance of understanding the advantages and limitations of high-density via usage. The key is understanding how to connect the signals and grounds through the board stackup. It is also essential to understand what is needed to provide the proper thermal connections between the ICs and ground planes.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Test Engineer
Target audience:  Beginner, Intermediate, Advanced
12:00 p.m to 1:00 p.m.
.  Free Lunch on Exhibit Floor


1:30 p.m. to 2:30 p.m.
19 .  Precision in Design: A Course on Strategic Design PCB Assembly
Speaker: , Tomas Chester

Effective printed circuit board (PCB) design extends beyond the meticulous consideration of layer stackup and appropriate PCB materials; it equally hinges on the strategic integration of assembly elements. Recognizing the pivotal role that assembly processes play in the manufacturability of a board, this course provides participants with a comprehensive understanding of the intricacies of assembly procedures. By immersing attendees in the nuances of the assembly process, this training empowers them to adeptly navigate the feedback loop, thereby guaranteeing the triumph of present and forthcoming designs.

The course will delve into the following aspects of assembly:

  • Small components and stencil requirements
  • Designing with thermal relief and why
  • Typical assembly issues and how designers can fix them.

This course imparts theoretical knowledge and reinforce learning through practical application. With instances of failures and conducting in-depth analyses of their root causes, participants gain valuable insights into preemptive strategies. Armed with this knowledge, they will be able to proactively mitigate potential issues, ensuring a resilient and successful approach to their current and future designs.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience:  Beginner, Intermediate, Advanced
1:30 p.m. to 3:30 p.m.
20 .  A Case Study on the Performance and Reliability of New Low-Cost and Sustainable PCB Materials for Immersion-Cooling Computer Systems
Speaker: Dan Liu, Alibaba Group, and Wayne Wang , Shennan Circuits

This study focuses on developing low-cost, sustainable new printed circuit board (PCB) materials for computer systems operating in immersion-cooling environments. As cloud service providers transition data centers from air cooling to immersion cooling, the demand for PCBs suitable for such environments increases. Immersion cooling offers significant advantages over air cooling, including lower and more stable operating temperatures (30-50°C), humidity-free, and a non-combustible environment (oxygen-free). These conditions are particularly beneficial for PCB materials like copper-clad laminate (CCL).

Leveraging these benefits, we have developed customized CCLs for immersion-cooling computer systems.

Our strategy for new CCL material development includes:

  1. Leveraging lower and more stable operating temperatures (30-50°C). Signal integrity (SI) performance requirements are more easily met with CCL in immersion. Unlike air-cooling conditions, which often require additional advanced polyphenylene oxide (PPO) added to CCLs to meet SI performance at higher temperatures (up to ~10°C), we aim to reduce PPO content in new CCL resins and explore alternatives to replace PPO with more readily available materials for immersion CCLs.
  2. Leveraging humidity-free. The need for moisture absorption resistance is more easily addressed in immersion. In air-cooling conditions, halogens like bromine (Br) and chlorine (Cl) are added to enhance moisture resistance. We propose reducing Br and Cl in immersion CCLs.
  3. Leveraging non-combustible environment (oxygen-free). Without flammable conditions in immersion, meeting UL flammability requirements becomes more straightforward. Since Br and Cl are typically used to improve flammability resistance in air-cooling conditions, we plan to further reduce their proportions in immersion CCLs.

Comprehensive testing of the new immersion CCLs and PCBs includes:

  1. Immersion CCL performance and reliability tests:
    • Moisture absorption rate
    • Dielectric constant (Dk) changes after immersion
    • Dissipation factor (Df) changes after immersion
    • Reliability after immersion
  2. Immersion CCL PCB SI performance and reliability tests:
    • Insertion loss measurements at different temperatures
    • Insertion loss before and after immersion
    • Reliability tests including interconnect stress test (IST), accelerated thermal cycling (ATC), and conductive anodic filament (CAF), among others.

In conclusion, this case study demonstrates the potential benefits of new CCL materials in immersion-cooling environments. Immersion-cooling not only provides advantages to data centers but also enables the use of cost-effective, sustainable new CCL materials, reduces the use of environmentally harmful substances, and decreases the overall carbon footprint of PCB development.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, CEO/COO/Sales/Marketing
Target audience:  Beginner, Intermediate, Advanced
1:30 p.m. to 3:30 p.m.
21 .  Routing and Termination of Lines to Control Signal Integrity
Speaker: Rick Hartley , RHartley Enterprises

Virtually all ICs used in digital circuits today have very fast rise time outputs, including many previously slow microcontrollers. Traces on boards with fast rise and fall times are referred to as high-speed transmission lines. Many items cause signal integrity issues in such lines. One associated set of contributors to SI problems is lack of proper impedance control, routing and termination. Understanding a few simple concepts can take a circuit from failure to success and understanding the concepts well can also reduce cost and layer count of PCBs.

This two-hour course will discuss and define:

  • When does a routed line become “high -speed?”
  • Movement of energy in transmission lines
  • Behavior of lumped vs. distributed length transmission lines
  • Incident wave vs reflected wave switching of IC loads
  • The effect on signal integrity of improper trace routing.
  • Best line termination schemes, including optimum resistor value
  • Matched circuit timing, with proper line length control.
Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience:  Beginner, Intermediate
5:00 p.m. to 6:00 p.m.
Reception on Exhibit Floor
Speaker: sponsored by Cofactr and EMA Design Automation ,


9:00 a.m. to 10:00 a.m.
F1 .  Panel: Engineering Knowledge Gaps
Speaker: ,


Who should attend: 
Target audience: 
9:00 a.m. to 10:00 a.m.
F2 .  Panel: AI in Electronics
Speaker: Moderator: Phil Marcoux ,

Artificial intelligence is quickly becoming a force in ECAD and electronics manufacturing. Will the intelligence in these tools supplant or accentuate today’s workforce? And how must the industry adapt to the changes? This is intended to give a snapshot of where we are, what’s feasible, and the forecasted timeline for implementation, straight from the companies that are driving the technology.

Who should attend: 
Target audience: 
10:00 a.m. to 11:00 a.m.
F3 .  AI and PCB Design: Where are We and Where are We Going?
Speaker: Matthew Leary , Newgrange Design

There is much talk about how AI will be impacting our future. This presentation will pull together some of the current thinking about AI from different industry experts with the goal to provide PCB designers information and hopefully some guidance about how we expect AI to impact PCB design in the two-, five- and 10-year timelines.

Key topics to cover:

  • Define/distinguish among automation, AI, generative AI, LLMs
  • The latest thinking on AI from major CAD players like Altium, Siemens (Mentor), Cadence, and Dassault Systèmes
  • How AI will affect the day-to-day work of the PCB designer
  • Does AI pose an existential threat to the profession of PCB design?
  • How today’s PCB designer can best prepare to be ready for the changes that AI will bring to the industry
  • How we protect IP in an AI environment
  • How each company/designer will bring unique IP to their AI integration.

It is important to note that this is a speculative talk based on some of the latest information available. Information about AI is changing rapidly. Some companies are willing to disclose only certain things that they are working on to the public. The goal is to educate and try to shed light on this rapidly developing, important influence to our industry with the intent that this will help us take a step forward together to make good decisions about our careers and how to best integrate new tools and features into our work to get optimal productivity and career gains.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience:  Beginner, Intermediate, Advanced
10:00 a.m. to 11:00 a.m.
F4 .  “Copper Pours” on PCB Signal Layers
Speaker: Rick Hartley , RHartley Enterprises

Debate is ongoing among many printed circuit design engineers about the use of copper pour segments in or on some layers of PCB. Some say copper pours can increase crosstalk, change impedance of transmission lines, increase EMI, or have an impact on power delivery, etc. Others say that the opposite is true. This session will discuss the “real” impact, good and bad, of copper pour segments on signal layers of PCBs.

This new one-hour course will discuss and define:

  • Reasons to put copper pours on signal layers
  • Should copper pours always connect to ground?
  • Measured impact of pours on impedance of lines
  • Measured impact of pours on energy coupling
  • Measured impact of pours on power delivery
  • Impact of copper pours on PCB manufacturability.
Who should attend:  PCB Designer/Design Engineer, System Engineer, Hardware Engineer, SI Engineer
Target audience:  Beginner, Intermediate, Advanced
11:00 a.m. to 12:00 p.m.
F5 .  Keynote
Speaker: ,


Who should attend: 
Target audience: 
12:00 p.m. to 1:00 p.m
Free Lunch on Show Floor
1:30 p.m. to 2:30 p.m.
F6 .  PCB Cost Drivers
Speaker: Ramon Roche , NCAB Group

Many aspects of a printed circuit board (PCB) determine its cost. The specifications drive the manufacturing process. In turn, this affects PCB price and sustainability.

This presentation provides insight of how PCBs are priced according to the fabrication drawing and Gerber data. Hard cost drivers, such as size, material, and build complexity cannot always be changed, but could have a bigger impact on the cost. Soft cost drivers like over-specification, lead times, and transportation may also have a great effect on the price. An understanding of the cost drivers will help engineers plan a more sustainable PCB for the future.

Who should attend:  PCB Designer/Design Engineer, CEO/COO/Sales/Marketing
Target audience:  Intermediate
1:30 p.m. to 3:30 p.m.
F7 .  The Most Common Issue Seen in Incoming Designs in PCB Fabrication
Speaker: Mike Tucker, Millennium Circuits, and Ray Fugitt , DownStream Technologies

In preparation for this presentation, we talked to many of the largest PCB manufacturers in the US and abroad. We then developed a list of the most common errors found on incoming designs. We look at each of the errors and discuss ways to find them before the designs are sent out for manufacturing. Methods we will look at include netlist comparison, design for manufacturing, and design rule analysis. We also talk about proper documentation needed for PCB manufacturing. We encourage attendee participation and ask folks to bring their challenges for discussion. After this seminar, the PCB designer will take back some knowledge to better assist them in using their existing tools in the market to produce better and more accurate designs.

Who should attend:  PCB Designer/Design Engineer, Fabricator Engineer/Operator
Target audience:  Beginner, Intermediate, Advanced
2:30 p.m. to 3:30 p.m.
F8 .  Nuke the Netlist
Speaker: Terry Hoffman, Cisco Systems, and Dana Korf, Nano Dimension ,

A process engineer responsible for a process with a long-term defectivity of 950,000dppm (95% scrap rate) would not last long in that role. A car company delivers a new car to a buyer where the buyer had to complete the design and send a list of changes back to the supplier proposing modifications so it would start and correct the car because some of the features do not work per the advertising description.

This describes the state-of-the-art of design data transfer in the printed circuit board industry. A PCB data package contains multiple files that are sent with incomplete, erroneous, and conflicting specifications. Bad files are routinely sent that impede creation of production files while resolving the issues.

This session will discuss this issue, focusing on one of the most erroneous files, the 35-year-old IPC-D-356 netlist. The problem will be described, discuss why industry standards are part of the problem, and how it has been resolved by using the industry standard IPC-2581 data format. We will also present a revolutionary format using an intelligent netlist for three additional PCB fabrication inspection processes.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, Fabricator Engineer/Operator
Target audience:  Intermediate
4:00 p.m. to 5:00 p.m.
F9 .  PCB and Circularity
Speaker: Ramon Roche , NCAB Group

As members of the electronics manufacturing industry, we often discuss the issue of material circularity, especially when it comes to printed circuit boards, and whether they can be recycled or created more sustainably.
The session will delve into topics ranging from material circularity in PCBs, to the environmental impact of technology, and the potential recyclability of the PCB product itself which NCAB has tested with customers. During this year we will join forces with some German labs and EMS companies to test how those materials perform in real use cases in terms of soldering processes, long-term reliability, and whether the material meets IPC Class 2 and 3 requirements after soldering.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience:  Beginner, Intermediate
4:00 p.m. to 5:00 p.m.
F10 .  Panel: UHDI: From Design to Manufacturing
Speaker: ,


Who should attend: 
Target audience: 
9:00 a.m. to 12:30 p.m.
22 .  How PCB Design Affects Fabrication
Speaker: Paul Cooke , Ventec

This course will walk the audience through the entire multilayer PCB fabrication process, making stops along the way to explain how PCB design requirements affect the numerous fabrication steps and if/how the finished product can meet the intended quality and reliability requirements. A detailed explanation will be given for each of the process steps and how that step affects quality and reliability.

Key topics to cover:

  • Design requirements, with an explanation of the dos and don’ts of how they affect fabrication and impact yields
  • Process controls adopted by the fabricator to ensure maximum yields and quality are maintained during each step of fabrication
  • Pros and cons of variables available to the designer:
    • Solder mask
    • Surface finish
    • Materials selection
    • Copper weights
    • Feature size, etc.

The course also looks at fabrication drawing specifications and how they can affect yield, cost, quality and reliability.

Who should attend:  PCB Designer/Design Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience:  Beginner, Intermediate, Advanced
9:00 a.m. to 12:30 p.m.
23 .  PCB Design for Engineers
Speaker: Susy Webb , DesignScience

Many engineers are now required to design their own PCBs, but have not had the benefit of learning the particular needs of the electronics, signals, placement, routing and manufacturability in those boards.
This class will feature an overview of the processes of board design from an engineering perspective. To begin, we will have a conversation about the electronics and physics involved and why controlling rise time, field energy, and transmission lines is extremely important to the signals on the board. Placement will be discussed next, with some of those topics including order, flow and setting up potential routing to come. The planes and stackup structure play a major role in the quality of the design and impedance control, especially if the design is high-speed; and plane and capacitor placement are a large part of power distribution as well. The way signals are routed and how their return current is set up is critical to performance.

Also discussed:

  • Fanouts
  • Grids
  • Signal flow from layer to layer
  • Layer paired routing and spacing.
  • HDI technology can be a huge benefit to dense boards, fine-pitch parts and BGAs, so we will go over their setup and routing.

All these topics will include information on signal integrity, EMI and impedance control, to make a board that works well from the first build. Many aspects of making a board manufacturable also help to make it less expensive, so an examination of that will wrap the technical things up, followed by information on the pros and cons of hand routing vs. autorouting and impact on board quality.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience:  Beginner, Intermediate
10:00 a.m. to 12:00 p.m.
24 .  Signal Attenuation in Very High-Speed Circuits
Speaker: Rick Hartley , RHartley Enterprises

In all high-speed/high-frequency circuits, signal integrity is dependent on several variables, all of which accumulate to impact the noise budget of the circuit. With very high-speed circuits, an even larger number of issues come into play, and all the effects are more extreme. Problems can be driven by design deficiencies, some by the physical structure and design of the ICs, and still more are driven by the PCB’s copper style and base material parameters.

This two-hour course will discuss and define:

  • Signal noise budgets and attenuation basics
  • Signal jitter and inter-symbol interference
  • Basics of transmission line discontinuities
  • Cause and effect of ground and Vcc bounce
  • Cause of skin effect and loss tangent issues
  • Impact of pre-emphasis and equalization
  • Via stubs and cost-effective solutions.
Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience:  Intermediate, Advanced
10:00 a.m. to 3:00 p.m.
25 .  Introduction to Signal Integrity/High Speed PCB Layout
Speaker: Keven Coates , OnwardAir

Why does what you see on the oscilloscope not look like a square wave? At today’’s speeds, traces behave very differently from what we were taught in college. This is a presentation on high-speed basics that helps make the subject intuitive in a different way. Learn about how frequency affects propagation, transmission line flow, impedance, noise, and reflections with easy-to-understand animations and analogies to understand this subject on a deeper level. Redone this year with more examples of good/bad layout.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test Engineer
Target audience:  Beginner
10:00 a.m. to 3:00 p.m.
26 .  The Basics of Rigid Flex Design
Speaker: John Watson , Altium

This presentation examines the basic design principles required to design a rigid-flex PCB. We first look at the definition, purposes, and uses of rigid-flex PCBs. This design technique is particularly useful in applications where space is limited and the circuit needs to conform to a non-planar or three-dimensional shape. We look at how combining rigid and flexible circuitry within a single board allows for cost savings in the manufacturing process.

  1. Definition: Rigid-flex PCBs consist of rigid and flexible board areas interconnected through plated holes. The rigid sections maintain stability and support components, while the flexible areas provide the necessary flexibility for folding or bending the board.
  2. Applications: Rigid-flex PCBs are commonly used in applications where traditional rigid boards or flexible circuits alone may not meet the requirements. Examples include aerospace, medical devices, wearables and other electronic devices with complex form factors.
  3. Design considerations: Designing rigid-flex circuits requires careful consideration of mechanical, thermal, and electrical factors. The board’s flexibility must be balanced with the need for rigidity in certain areas, and bending radii should be adhered to prevent damage.
  4. Layer stackup: The layer stackup involves alternating rigid and flexible layers. This permits the necessary combination of structural integrity and flexibility. Copper layers, dielectric materials, and adhesive layers are carefully chosen to meet the mechanical and electrical requirements.
  5. Bend radius: The bend radius is a critical factor in rigid-flex design. It defines the minimum radius at which the flexible part can bend without damaging the internal layers or causing performance issues. Designers must adhere to specified bend radius guidelines provided by manufacturers.
  6. Flex-to-rigid transition: The transition between rigid and flexible areas involves carefully designed bending zones. These zones include gradual transitions with curves or accordion-like folds to prevent stress concentration and ensure reliability during flexing.
  7. Component placement: Component placement plays a crucial role in rigid-flex designs, allowing for reliable electrical connections between the rigid and flexible sections. Proper placement and reinforcement are essential to prevent mechanical failures at these points.
  8. Material selection: Material choices are crucial in rigid-flex design. Selecting flexible substrates, adhesives, and coverlay materials should align with the environmental conditions, thermal requirements, and overall performance expectations.

In conclusion, designing rigid-flex PCBs involves a careful balance of mechanical and electrical considerations to achieve a reliable and functional product in applications demanding flexibility and three-dimensional form factors.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, Fabricator Engineer/Operator
Target audience:  Beginner
10:00 a.m. to 5:00 p.m.
27 .  Power Delivery System (PDS) Design
Speaker: Lee Ritchey , Speeding Edge


Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator
Target audience:  Intermediate, Advanced
12:00 p.m. to 1:00 p.m.
Lunch-N-Learn (Thursday Conference Attendees Only)
1:30 p.m. to 3:30 p.m.
28 .  DDR5 Through the Eyes of the Designer
Speaker: Charlene McCauley and Terrie Duffy , McCauley Design Group

How to reach the maximum capacity interactions between processor and memory using the new Dell/Jedec CAMM connector. The demand for speed is here and now from media, CAD, 3-D design, scientific research and data analysis, AI, and machine learning. This presentation aims to explore through the eyes of the designer the key design challenges when routing DDR5, from processor and memory placement considerations to maximum speed and performances.

  1. What is the CAMM connector on external modules, not motherboard
  2. DDR5 vs. previous DDR
  3. LPDDR vs DDR
    a. Voltage differences
    b. DRAM layout difference
    c. Constraint differences
  4. Placement and pattern of DRAMs
  5. Pattern of DRAM placements
  6. To mirror or not
  7. Sharing command addresses
  8. Length matching philosophies. SODIMM vs CAMM
  9. Offsets for length matching
  10. Special cases of length matching
  11. Single channel/dual channel
  12. Signal impedance
  13. Planes.
Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience:  Intermediate, Advanced
4:00 p.m. to 6:00 p.m.
29 .  Designing for Reliability: Design Choices have Cleanliness Consequences
Speaker: Caleb Buck , Nidec Aerospace

You’ve done it! You have created the perfect design that will meet all your customer’s signal integrity requirements! However, you were not aware that your design choices have cleanliness consequences and now your customer informs you that your “perfect design” has failed in the field. Their investigation finds that this failure was caused by flux residues that grew dendrites, causing a short circuit. In this situation it is easy to point the finger at whomever assembled the PCBAs, but a number of design choices likely could improve the cleanability of a design.

In this presentation you will learn how to design for reliability by making proactive design choices that will greatly reduce the failure rate of a design in the field. You will learn about the various PCB cleanliness failure modes and how end-use environmental factors contribute to system reliability. We will also explore how to find cleanliness failures when things don’t go as planned.

The majority of this presentation will focus on specific design choices that can be made and how exactly those design choices help or hurt the cleanability of a design.

Topics covered:

  • Cleanliness verification methods
  • Flux selection
  • Component geometry
  • Layout for cleanliness techniques
  • Conformal coating
  • Cleaning methods.

SIR test results from my ongoing PCB cleanliness case study will be shared throughout the presentation as objective evidence for these design concepts. What you will learn:

  • How cleanliness failures occur
  • How to avoid failures by being proactive in design choices
  • How to design for reliability.
Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, Test Engineer, Assembly Engineer/Operator
Target audience:  Beginner
4:00 p.m. to 6:00 p.m.
30 .  Ask the Flexperts with Lessons Learned
Speaker: Mark Finstad, Flexible Circuit Technologies, and Nick Koop, TTM Technologies ,

“This course covers the entire gamut of flexible and rigid-flex circuits from two of the most recognized names in the flexible circuit industry: Mark Finstad (co-chair of IPC-2223) and Nick Koop (co-chair of IPC-6013).

Topics covered include:

  • Mechanical design/material selection
  • Cost drivers
  • Bending and forming concerns
  • Testing
  • Issues unique to rigid-flex.

This course also includes a complete virtual plant tour of a flexible circuit manufacturing facility to help attendees understand the manufacturing processes. Throughout the presentation, the instructors will share real-life stories of flexible circuit applications gained over 35+ years in the industry. Some are success stories, others not so much, but all provide excellent lessons learned. The instructors also welcome and encourage questions and enjoy wandering off-course with lively interactive discussions on specific topics from the class.”

Who should attend:  PCB Designer/Design Engineer, System Designer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience:  Intermediate, Advanced
4:00 p.m. to 6:00 p.m.
31 .  Avoiding PCB Respins, Reducing Cost and Time to Market
Speaker: Syed Ubaid Ali Warsi , Wavetroniks

How often do do we receive a schematic from the electrical engineer and the PCB layout starts in haste? Weeks of effort are spent, and the layout completed based on our own understanding, but during the final review we realize the design doesn’t comply with the fundamental requirements, as they were never properly conveyed and documented. What now? It’s time for frustration and probably a design respin. This scenario can become worse if the issues are raised after fabrication and assembly.

Ever-increasing rising and falling clock edges of an IC demand an innovative and smart design approach rather than a conventional approach. In this session, we’ll discuss the best practices/standard operating procedure to overcome this situation effectively and efficiently.

What you will learn:

  • The collaborative approach to involve major stakeholders early in the design phase
  • What kind of documents and meetings are needed before kicking off the PCB layout.
  • How to acquire and document the mechanical requirements
  • How to ask the EE to make the system block diagram effective and meaningful for the PCB designer
  • How to understand the electrical side of the design and incorporate those insights into the layout.
Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience:  Beginner, Intermediate, Advanced
4:00 p.m. to 6:00 p.m.
32 .  System Mechanical Design to Control EMI
Speaker: Rick Hartley , RHartley Enterprises

EMI occurs because some mechanical structure, within or attached to the system, is capable of resonating and radiating stray electro-magnetic field energy. Those mechanical structures can be a cable attached to the enclosure, items near the circuit, a part of the metal chassis, a slot in the chassis or a portion of one of the circuit boards in the system. Knowing how to control these structures so they are not capable of supporting resonance and radiation is the key to success.

This two-hour course will discuss and define

  • Determining max frequency of a system
  • Antenna “in” and “on” PCBs and enclosures
  • Metal vs. plastic enclosures and shielding of circuits
  • Impact of slots and openings in enclosures
  • Impact of component placement and PCB shape
  • Extreme importance of I/O connector placement
  • Correct shielding of I/O cables.
Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience:  Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
33 .  Analog Measurements – Sensor Selection, Interfacing, and PCB Design Examples
Speaker: Ben Voigt and Nathan Christensen , Sparx Engineering

Analog sensors are in constant use, measuring the physical world as electrical data that is digitized and used to understand, optimize, and innovate. If analog engineering is allowed to become an afterthought in a world focused on IoT and digital interconnectivity, sensor data quality and reliability will become the performance-limiting “weakest link.” Whether reading pressure and temperature in piping at an industrial plant, optically sensing blood composition in a hospital, or providing motion feedback in robotics, every industry relies on these analog sensors.

Maybe you’ve wondered:

  • Should I use an RTD or an NTC or a thermocouple?
  • Should a 4-20mA circuit use 2, 3, or 4 wires?
  • Should I use 4-20mA, 0-5V, mV/V, SPI, I2C, or RS-485?
  • Will a sensor need additional electronics or will it work out of the box?
  • What circuits, components, and PCB designs work best to interface with the many different types of sensors?
  • Will my sensor work in an electrically noisy environment and how can I adjust board layout to improve my noise floor?

This session will provide the information to select and integrate analog sensors into new or existing PCB designs. Attendees will gain knowledge of how common analog sensors work, common types of these devices, their potential applications, and a breakdown comparison of the many sensor options.

Additionally, attendees will walk away with example circuits to interface with various sensors and learn best practices in PCB design to ensure high quality data capture. With a better understanding of where our digital data comes from, engineers, PCB designers, and leadership can make informed decisions to get the best sensor and the correct PCB design for the job at hand.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, CEO/COO/Sales/Marketing
Target audience:  Beginner, Intermediate
10:00 a.m. to 12:00 p.m.
34 .  PCB Stackups & Impedances
Speaker: Ryan Miller , NCAB Group

As printed circuit boards become more complex, so do the stackups. Some stackups require specialized materials and multiple drill cycles during manufacturing. This two-hour presentation gives engineers training on current industry standards and practices for stackups and impedances.

What we cover:

  • Insight to PCB materials
  • Stackup manufacturing process
  • Simple and complex stackups
  • Stackup design tips
  • Designing stackups with impedance traces (introduction to impedance traces, impedance structures, and specifications)
  • How materials and impedance traces work together to produce the specified impedance value
  • Impedance design tips for better signal integrity.
Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, SI Engineer
Target audience:  Beginner, Intermediate
10:00 a.m. to 12:00 p.m.
35 .  Designing Complex PCBs
Speaker: Stephen Chavez , Siemens

Designing complex PCBs is a multifaceted and challenging task that plays a pivotal role in the development of advanced electronic systems. This presentation explores the key considerations, methodologies, and emerging trends in the field of complex PCB design. The complexity of modern electronic devices demands intricate PCB layouts to accommodate high-density components, diverse functionalities, and stringent performance requirements. We will delve into the critical aspects of layout solvability, signal integrity and electromagnetic interference, power integrity and power distribution, thermal management, and manufacturability, emphasizing the need for a holistic and systematic approach.

We will also address the incorporation of EDA tools to enhance the efficiency and reliability of complex PCBs. As the demand for smaller form factors and increased functionality rises, designers face the challenge of optimizing space utilization while minimizing electromagnetic interference and signal crosstalk. We will explore strategies for mitigating these challenges, including the use of automation in placement and routing to include simulation and DfM tools.

Furthermore, we will discuss the role of collaboration between hardware and software teams in achieving successful complex PCB designs. The integration of design for manufacturability (DfM) and design for testability (DfT) principles is highlighted as essential for streamlining the production process and ensuring reliability of the final product. The evolution of Industry 4.0 and the Internet of Things (IoT) introduces new dimensions to complex PCB design, with considerations for connectivity, security and adaptability becoming increasingly important.

In conclusion, this presentation provides a comprehensive overview of the challenges and strategies involved in designing complex PCBs, emphasizing the interdisciplinary nature of the task and the need for a holistic design approach.

What you will learn:

  1. The three key perspectives of success in PCB design
  2. Increase productivity and proficiency with current/future EDA software (automation)
  3. Benefits of implementing best practices and the cost of doing nothing (remaining status quo).
Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience:  Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
36 .  Improving Circuit Design and Layout: Strategies for Enhanced Accessibility and Success
Speaker: Tomas Chester , Chester Electronic Design

In today’s rapidly evolving design landscape, engineers and designers face the challenge of delivering high-quality results efficiently. This seminar offers attendees actionable insights and practical examples to enhance their design processes, ultimately leading to improved project outcomes and reduced time spent on circuit, component, and layout knowledge acquisition.

Our seminar will delve into three key areas:

  • Project foresight for proactive decision-making
  • Leveraging multi-channel/multi-project design reuse for efficiency
  • Ensuring identical characterization throughout the development cycle for consistency.

We will cover a range of essential topics, including:

  • Efficient component and library creation for future and multi-project use
  • Simplifying schematic accessibility and reducing complexity
  • Strategies for effective printed circuit schematic and layout design, with an emphasis on verification and debugging
  • Procedural interactions that contribute to project success.

Attendees will leave with a toolkit for achieving design success, including:

  • Real-world design examples and experience with various project states
  • Methods for streamlining the verification and debugging processes
  • Insights into collaborative, multi-user perspectives that can enhance project outcomes.

Join to unlock the potential of your design process and take your projects to the next level.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Assembly Engineer/Operator
Target audience:  Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
37 .  Noise, SI, and EMI in Cables and Connectors
Speaker: Keven Coates , OnwardAir

Everyone talks about signal integrity in PCBs, but few circuit boards operate without external wiring. Whether it’s as simple as power wiring, as complicated as high-speed differential pairs or even worse, non-differential pairs, there are good and bad ways to use the connectors and cables available to us today.

This class will show how connectors and cables relate to signal integrity concepts:

  • How does the energy flow in the wiring?
  • What determines impedance in non-impedance-controlled wiring?
  • How many grounds do I need in the cable/connector?
  • How do I pick connectors?

It will go over practical examples showing the tradeoffs (since nothing is completely ideal). This class will shed new light on how we can apply the same signal integrity rules to wires and cabling as we do PCB layout.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience:  Beginner, Intermediate, Advanced
12:00 p.m. to 1:00 p.m.
Lunch-N-Learn (Friday Conference Attendees Only)
1:30 p.m. to 3:30 p.m.
38 .  PCB Embedded Inductor Technology
Speaker: Paul Yang , JOVE PCB

With the rapid development of artificial intelligence and autonomous driving technology, miniaturization, integration, and modularization are the general trend of electronic product design, especially in chip power supply. Designers are looking for higher efficiency, higher power density, better reliability, and smaller package sizes.

The inductors of tertiary power modules that power CPUs and GPUs usually occupy a large surface area, making it challenging to deploy more chips and small-sized resistors and capacitors. Thanks to the development of copper-iron co-firing integrated inductor technology, inductors can be embedded into the PCB and copper plating makes connections and fanouts. In some ways, it is the first packaging by PCB embedded technology, which can solve this problem well.

This talk will focus on the advantages of inductor embedded PCBs, key manufacturing technologies, reliability test, design rules, and typical product shows.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, System Designer, SI Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience:  Beginner, Intermediate, Advanced
1:30 p.m. to 3:30 p.m.
39 .  Launching Electronics with Confidence: A Guide to Successful Design Release
Speaker: Syed Ubaid Ali Warsi , Wavetroniks

In the dynamic realm of electronics, completing a PCB layout is just the tip of the iceberg. The real challenge lies in seamlessly signing off the design and generating the manufacturing release. The significance of having comprehensive documentation, thorough checklists, and strategic review meetings before any design release cannot be overstated.

In the fast-paced world of technology, where time to market is a decisive factor in product success, hasty design releases can prove to be detrimental. Organizations often face nightmares when crucial elements are overlooked. History provides cautionary tales, such as the downfall of giants like Kodak and RIM (Blackberry phones), underscoring the importance of timely product launches.

This session will explore the importance of comprehensive documentation, checklists, and thorough review meetings prior to design release.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Test Engineer
Target audience:  Beginner, Intermediate, Advanced
1:30 p.m. to 5:00 p.m.
40 .  Designing Boards with Today’s BGAs
Speaker: Susy Webb , DesignScience

Fan out and routing of today’s BGAs can be quite challenging! With the overall size of the parts increasing and the pitch between pads decreasing, it can be extremely difficult to get all the signals (and powers) into or out of the part at all, and especially without using many, many layers of the PCB.

If the designer uses creativity to set up patterns of signals and vias, the fanout can be completed for all the signals, while using the layers of the board efficiently. The signals will also need to maintain a good return path, signal integrity and EMI control, which complicates things more. These issues can be addressed with some thought and preparation that we will discuss. Additionally, there are manufacturing concerns that are unique to the newer BGAs because of their small pad sizes, the trace widths needed, and the small capacitors used.

This presentation will discuss:

  • Signals and via patterns
  • Fanout completion
  • Signal return paths
  • Signal integrity and EMI control
  • Manufacturing concerns unique to newer BGAs
  • Choosing effective BGAs
  • Cap placement
  • Power and stackup information
  • Grid systems for through hole and microvia fanout.
Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, SI Engineer
Target audience:  Intermediate
1:30 p.m. to 5:00 p.m.
41 .  PC Board Design for Optimum Manufacturability
Speaker: Rick Hartley , RHartley Enterprises

Many engineers believe the cost of the bare PCBs and assemblies is purely a function of board size, thickness, number of layers, spacing between features, etc. Part of that is true, but many other factors drive cost and reliability. Even more important, many PCB design issues determine the quality of bare boards and assemblies, such as “where” the copper is located as well as copper density, parts placements, how the board is routed, balanced PCB stack-up, feature sizes, etc.

This course discusses and defines:

  • Copper density, balance, location, PCB stack-up, etc.
  • Cost impact of PCB size and shape vs. fabrication panel sizes
  • The many PCB feature shapes and sizes vs. copper weight, thickness, etc.
  • Design methods to minimize cost-adders to the bare board and assembly
  • Understanding design for manufacturability at all levels
  • How to avoid design modifications from fab and assembly houses
  • Associated IPC standards and specifications.
Who should attend:  PCB Designer/Design Engineer, Hardware Engineer
Target audience:  Beginner, Intermediate, Advanced