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2019 Day-by-Day Conference Program

Monday Sept 9th

Monday, September 9th
8:00 a.m.
Conference Coffee Break, sponsored by Sierra Circuits
8:30 a.m. – 12 noon
1: Developing an AI Strategy to Address a CAD/CAM Design Process Bottleneck
Speaker: Daniel Smith, Raytheon Missile Systems

This seminar is for those tasked to create custom user-ware for their company to address a CAD/CAM design process "bottleneck" to create a repeatable and cost-effective solution. Participants will walk through a real design problem, developing a "correct by construction" AI (artificial intelligence) strategy before they write their first line of code. Although there will be a course book that walks through the entire process, all students are encouraged to bring their own laptops, as actual code samples will be provided. (Please have MS Excel and Python 3.* already installed). Note: Registration may be limited due to the size of classroom provided.

Who should attend: PCB Designer, Design Engineer, Software Programming/Scripting
Target audience: Advanced
9:00 a.m. – 12 noon
2: The Complete Guide to Characterizing Transmission Lines with a TDR
Speaker: Dr. Eric Bogatin, Teledyne LeCroy

TDR is the standard tool used to characterize transmission lines. The first and most important figure of merit a TDR measures is the characteristic impedance of the transmission line. With careful calibration, it is also possible to extract the second important figure of merit, the time delay. With a simple test vehicle, the TDR can also provide figures of merit for the Dk of the laminate and even resistive losses. But there is so much more the TDR can reveal about the properties of transmission lines: printed circuit board traces, flex interconnects and cables. In this half-day workshop, using live demonstrations and examples, we will illustrate the principles behind the TDR and how to interpret measurements of both single-ended and differential interconnects. We will answer some of the perplexing questions, such as what is the impedance a TDR measures? At what frequency does a TDR measure the impedance? What’s the difference between a TDR measurement of impedance and a VNA measurement of impedance? What rise time do I need? How long a line do I need to get the differential impedance? What does resolution mean, and how does it vary with rise time? How do I engineer a clean launch, and do I care? What is the difference between the single-ended impedance and the differential impedance of loosely and tightly coupled differential pairs? How do I measure the differential impedance of a twisted pair cable when I don’t have a ground connection? Why does the TDR trace sometimes ramp out, and what do I take as the characteristic impedance in such cases? How do I judge the accuracy of a TDR measurement?

Who should attend: PCB Designer, Design Engineer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator, Test Engineer
Target audience: Beginner, Intermediate
 
3: Ask the Flexperts – Flexible Circuit Design through Test with Lessons Learned
Speaker: Mark Finstad, Flexible Circuit Technologies, and Nick Koop, TTM Technologies

This course will cover the entire gamut of flexible and rigid-flex circuits from two of the most recognized names in the industry: Mark Finstad (co-chair of IPC-2223) and Nick Koop (co-chair of IPC-6013). Topics covered will include mechanical design/material selection, cost drivers, bending and forming concerns, testing, and issues unique to rigid flex. Throughout the presentation, the instructors will share many real-life stories of flexible circuit applications gained over 35+ years in the industry. Some of these are success stories, others not so much, but all provide excellent lessons learned. The instructors also welcome and encourage questions and enjoy “wandering off course” with lively interactive discussions on specific topics from the class.

Who should attend: PCB Designer, Design Engineer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate
9:00 a.m. – 5:30 p.m.
4: PCB Stackup Design and Materials Selection
Speakers: Bill Hargin, Z-zero

This tutorial will guide design teams through the process of evaluating and selecting the right laminate for a design, creating PCB stackups that meet the requirements of complex, multilayer boards that work right the first time, within budget, and with reproducible results across multiple fabricators. The course will go into detail on tradeoffs between loss and cost, including dielectric loss, resistive loss, surface roughness, as well as glass-weave skew. After attending this course, students will be knowledgeable about PCB laminate tradeoffs, the laminate materials market, and the process of troubleshooting problematic stackup designs. Attendees will also be exposed to cost-effective strategies for controlling loss and glass-weave skew.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, Test Engineer
Target audience: Beginner, Intermediate, Advanced
 
5: The Basics of PCB Design for Novices and Engineers
Speaker: Susy Webb, Design Science

Technical sessions at conferences often emphasize the latest techniques and technologies, but those classes are often too in-depth for a novice designer, and don’t speak to the questions from the engineers who need to design their own boards. This class features an overview of the entire process of designing a board, from start to finish. We will begin with creating manufacturable footprints that meet the IPC specs. Then we will address some common placement techniques like floor planning, color coding, flow, orientation, and placement to set up routing. We will follow that with a discussion of planes and stackups and how to configure them to get the best results for parts and signals. Next, we move on to some fanout and routing techniques that are helpful for completing the design connections to meet the number one design rule: good electrical performance. We will complete the process by discussing manufacturability concerns that can be affected by the way the board is designed, some finishing issues, and sending out good documentation the manufacturers can easily understand and use.

Attendees will learn recommended minimum standard set for designers, standards that affect the design of printed boards, and design changes that affect manufacture and reliability of a product.

Who should attend: PCB Designer, Design Engineer, Hardware Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate
 
6: Advanced PCB Fabrication and Defects
Speaker: Paul Cooke, FTG

This course will address advanced problem solving of printed wiring board defects. Defects such as interconnect separation, delamination, wedge voids, plating folds, microvoids, surface pitting, and hole wall pull-away carry significant costs. Many are difficult to solve because the root cause may not be readily apparent, and multiple factors may contribute. This course will explore the most intricate of these factors and how the interrelationship of up- and downstream processes contribute to scrap product. What effect does drilling have on hole wall quality and the subsequent metalization process? Participants will learn how to recognize problems like this and take corrective action. The course will explore a myriad of electrodeposition defects, such as mouse bites, pitting, and domed or crown plating. Solderability and assembly-related issues such as outgassing, black pad, creep corrosion and blow holes will also be discussed.

Participants should have some knowledge of the PCB fabrication process. In addition, new topics will be presented, including pad cratering, microvia interfacial fracture and reliability testing. The course will conclude with a discussion on imaging, including liquid-photoimageable solder masks. Strategies to solve solder mask peeling, poor circuit trace coverage, skips, bubbles, and poor adhesion in nickel gold plating will be discussed. Solder mask equipment and its effect on solder mask quality will be explored.

The course is designed in two half-day sessions. Part 1 will cover innerlayer treatment/MLB fabrication, opens, shorts, delamination, other lamination/MLB issues, material selection, misregistration, chemical treatments (oxide, oxide alternatives); PTH (electroless copper/metalization issues such as PTH defects, voids, ICD, hole wall pull-away); metalization of flex and rigid-flex circuits. Part 2 will cover electroplating-related issues, mouse bites cosmetic defects, copper defects, barrel cracking, dog-boning, plating distribution and relationship to PCB reliability; solder mask issues such as final finishes, black pad-interfacial failures (i.e., brittle fracture), trench etch, champagne bubble and other surface finish defects; solderability failures and final finishes, pad cratering, via filling issues, copper erosion, failure analysis and reliability. These courses are ideal for process engineers, engineering managers, those involved in printed circuit assembly, circuit board designers and those involved in purchasing circuit board and qualifying printed board fabricators. The offering will also benefit individuals looking to gain a much broader view of PCB-related defects.

Who should attend: PCB Designer, Design Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate
12 noon – 1:00 p.m.
LUNCH-N-LEARN, Sponsored by Summit Interconnect
1:30 p.m. – 5:00 p.m.
7: Effective PCB Design: Techniques to Improve Performance
Speaker: Dan Beeker, NXP Semiconductor

Tired of failing EMC certification over and over? Join the crowd. Shrinking IC geometries and resulting increase in switching speeds make designing compliant printed circuit boards more challenging than ever. We need a new design methodology to change this unacceptable status quo, one based on electromagnetic field physics. This training module presents a basic introduction to EM fields and provides guidelines for building successful, cost-effective printed circuit boards. This presentation includes example designs and test results.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
1:30 p.m. - 2:30 p.m.
8: Accelerate PCB Design Layout Using AI and Machine Learning
Speaker: Naveid Rahmatullah and Xiao-Ming Gao, Intel

This presentation introduces an efficient PCB layout router using artificial intelligence (AI) and machine learning (ML). As the complexity and variety of system on chip and IPs development keep increasing, the platforms used to validate silicon electrical and functional performances are becoming increasingly difficult due to time to market and costs constraints. To address these challenges, different types of interposers were designed to meet flexible validation requirements. However, the PCB interposer layout is very challenging due to irregular routing patterns and stringent signal integrity constraints. Existing autorouters are not able to address this issue effectively, and most routings must be performed manually. To accelerate the PCB layout process, AI- and ML-based smart routers using neural networks and genetic algorithms were developed and successfully tested on different kinds of interposer topologies. Comparison data show the AI router can drastically reduce the routing time from weeks to hours. The production-quality new router modules are currently under extensive testing.

Building on this success, we are further extending the AI router capability to handle other PCB topologies, such as power interposers, electrical validation platforms, and other general PCB layouts. Compared with traditional autorouters, for which algorithms do not make use of past design knowledge or effectively use available computing resources to expedite the completion rate, the AI router uses genetic optimization to concurrently explore the solution space and a pre-trained neural net to guide the router on the technology used. The algorithms built in massively parallel calculations can fully utilize the modern computing power such as multicore CPUs and GPUs such that multiple routing strategies can be evaluated in parallel and the optimal one chosen based on a performance matrix. Further, the new machine learning-based autorouter can learn those routing patterns from design to design under similar physical and electrical constraints and develop intelligence into the database. Its performance and power will evolve with time as more designs have been routed, validated and learned. The more designs it routes, the smarter it will be. Therefore, the proposed AI smart router will help not only significantly accelerate a large variety of PCB routings but also reduce resources and speed time-to-market.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced
1:30 p.m. – 3:30 p.m.
9: IoT (Internet of Things) PC Board Design
Speaker: Rick Hartley, RHartley Enterprises

Circuit boards for the IoT World (Internet of Things) are often driven by the need for low power dissipation, low cost (which drives very low layer count), moderate- to high-density and mixed-signal applications. This combination of needs can make PCB design an extreme challenge. Creating a one-, two- or four-layer board, with excellent signal integrity and low noise/interference and no EMI issues, can by itself be a serious challenge. This two-hour course will discuss how to understand when it is necessary to control impedance of lines, how to do it cost-effectively, proper setup of lines to keep circuit energy from spreading (preventing interference), even on a one-layer board, circuit grounding in low-layer-count boards, power distribution without the benefit of power planes, ground bounce, crosstalk with low-layer-count, and design to optimize manufacturability of low-layer-count PCBs.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate
 
10: From DC to AC - Power Integrity and Decoupling Primer for PCB Designers
Speaker: Ralf Bruening, Zuken EMC Technology Center

Supply voltages decrease with every new silicon generation, contributing as well to the goal of reducing power consumption of our electronics. Coupled with the resulting shrinking noise margins for these ICs, this defines increasing demands for the quality and stability of power distribution schemes of PCBs. Hence, tighter requirements and constraints from silicon vendors are defined for power distribution networks (PDN), which PCB designers follow, in conjunction with tighter decoupling schemes. Board real estate limitations, application-dependent restrictions (e.g., discrete package size allowance in automotive), and cost demands further complicate the game. To address these technical challenges, engineers need to evolve from working within a disconnected process to new or advanced design methodology with power-integrity and the demands of the PDN in mind. Using such a methodology and smart mechanisms to optimize the decoupling scheme can help ensure a design will meet the electrical specifications for power. In this two-hour workshop, the requirements and basics of PCB power distribution systems are explained in detail. The whole problem area range from DC (with aspects like IR-drop, DC voltages and current distributions) to AC with its phenomena (e.g., target impedance, decoupling, inductance) is covered. Topics like plate capacitance, loop inductance and cavity resonance are explained in detail but without deep math. Side effects to the signal integrity and EMC behavior of board structures are discussed using illustrated practical examples. The role of capacitors, their parasitic behavior and evolution in recent years are a major part of the workshop. Guidelines for a first order covering and resolving power integrity issues are provided, regardless of the PCB design and ECAD process. Simulation capabilities addressing power integrity during PCB design will be explained and demonstrated by slides in a generic vendor-neutral manner as a problem-solving approach. Silicon vendor support documents (e.g. constraint and spreadsheet tools) to address Power Integrity are introduced and discussed. Examples from various industries (e.g., automotive, industry automation, IoT) will complement the session with practical application experience.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
1:30 p.m. - 5:00 p.m.
11: Design, Fabrication and Assembly Process Principles for Flexible and Rigid-Flex Circuits
Speaker: Vern Solberg, Solberg Technical Consulting

Flex circuits typically replace the common hard-wire interface between electronic assemblies. Flexible circuits, however, have significant advantages over the hard-wired alternative because they fit only one way, eliminate wire routing errors, and save up to 75% on space and weight. The design guidelines for flexible circuits, although similar to rigid circuits, are somewhat unique. In essence, flex circuits furnish allow freedom of packaging geometry, while retaining the precision density and repeatability of printed circuits. Because the flex-circuit conductor patterns can maintain uniform electrical characteristics, they contribute to controlling noise, crosstalk, and impedance. Flex circuits will often be designed to replace complex wire harness assemblies and connectors to further improve product reliability. During the half-day tutorial program, participants will have an opportunity to review and discuss the latest revision of IPC-2222 and IPC-2223, “Sectional Design Standard for Flexible Printed Boards,” that includes base material sets, alternative fabrication methodologies and SMT-on-flex assembly processes. The workshop will also furnish practical flex circuit supplier DfM recommendations for ensuring quality, reliability and manufacturing efficiency. Topics of discussion: 1. Applications and use environment (commercial/consumer, industrial/automotive, medical/aerospace); establishing end use criteria 2. Designing flexible and rigid-flex circuits (flex circuit outline planning; circuit routing and interconnect methodologies; fold and bend requirements; SMT land pattern reinforcement criteria). 3. Material and SMT components (IPC standards for flex and rigid-flex dielectrics; base material and metallization technologies; selection criteria for SMT components; SMT land pattern development). 4. Assembly processing of flex and rigid-flex circuits (dimensioning and tolerance criteria; palletized layout for inline assembly processing; SMT assembly process variations and methodologies alternative joining methods for flexible circuits).

Who should attend: PCB Designer, Design Engineer, System Designer
Target audience: Beginner, Intermediate
3:00 p.m. – 5:00 p.m.
12: How to Fight Magnetic Noise Gremlins
Speaker: Keven Coates, Geospace Technologies

Have you ever had a noise-sensitive circuit and tried to find the noise source? Even after you completely encased sensitive portions in all sorts of shielding, you still had noise? It’s very possible this is magnetic noise. Lower frequency magnetic fields can’t be contained and shielded against in the same way electric fields can. In this presentation, hear about the author’s nine-month long battle with a specific magnetic noise issue, the best tools to fight it, twisted pair, current loops, and the best ways to test for and defeat magnetic noise in your designs. New this year is more on how electric fields compare.

Who should attend: Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced
3:30 p.m. – 5:30 p.m.
13: Signal Attenuation in Very High-Speed Circuits
Speaker: Rick Hartley, RHartley Enterprises

In all high-speed/high-frequency circuits, signal integrity depends on a number of variables, all of which accumulate to impact the noise budget of the circuit. With very high-speed circuits, an even larger number of issues come into play, and all the effects are more extreme. Some problems are driven by design deficiencies, some by the physical structure and design of the ICs, and still more are driven by the PCB's copper style and base material parameters. This course will outline all the effects impacting signal integrity at very high-speeds and will detail such items as via stubs, jitter, inter symbol interference, impact of copper style on skin effect, loss tangent, impact of layer change during routing and other major signal integrity concerns, as well as the impact some of these items have on timing and the Y-axis attenuation of signal eyes. Also discussed will be solutions to these issues, including some new high-speed base materials.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Intermediate, Advanced

Tuesday Sept 10th

Tuesday, September 10th
8:00 a.m.
Conference Coffee Break, Sponsored by Sierra Circuits
8:30 a.m. – 12 noon
14: The Complexities of Fine Pitch BGA Design
Speaker: Susy Webb, Design Science

Designing with BGAs is much more challenging than in the past! The ball pitches are going down, and the total pin counts and package sizes are going up, making everything more complex. With those changes, the signal integrity and EMI issues become more profound, the fanout and routing are much more challenging, and the power connections and thermal issues are more difficult. Add to that the manufacturing concerns that have surfaced from small pad openings and tiny capacitors, and the designer faces some complex issues. In this presentation, we will discuss all those things and more, including choosing effective BGAs, placement for components and caps, grid systems for parts and routing, some fanout possibilities, and some manufacturing issues unique to these kinds of designs. This class has lots of illustrations and examples!

Who should attend: PCB Designer, Design Engineer, Hardware Engineer
Target audience: Intermediate
 
15: Moving Beyond SMT: Heterogeneous Assembly
Speaker: Phil Marcoux, PPM Associates

Density, speed and cost are the driving forces for most electronic products. For almost four decades SMT has helped meet these forces. Now a newer technology is moving up to take over. Heterogeneous technology is a collection of technologies combining packaged and non-packaged components with non-solder, compression, epoxy, and reflow attachment methods. The components may be placed on the substrates or in the substrates. Assembly may be performed by traditional SMT assemblers, IC package assemblers, or a hybrid organization. Challenges exist, but the benefits for early adopters have been profound. This seminar will cover the various assembly technologies, component packaging options, the most adoptive markets, substrate types, and design guidelines.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
 
16: Embedding Passive and Active Components: PCB Design, Fabrication Methodologies and Assembly Process Strategy
Speaker: Vern Solberg, Solberg Technical Consulting

Uncased active and passive component elements are candidates for embedding, but the process of selecting these components must be made early in the design process. Developers have realized that in addition to passive components, embedding one or more active die elements on an innerlayer of the circuit in close proximity to prepackaged semiconductor(s) mounted on the outer surface, electrical interface between components can be minimized, considerably improving functional performance. This closer coupling of key passive and active semiconductor elements will significantly reduce inductance, contribute to increasing signal speed, and lower overall power consumption. Some components are easy candidates for integrating into the substrate, while others may involve more complex processes and will be difficult to rationalize. And although a majority of the discrete passive and active devices may remain mounted on the outer surfaces of the circuit board, embedding a majority of the resistor functions and one or more silicon-based semiconductor elements within innerlayers of the structure can enable greater utilization of the PCB’s outer surfaces. This half-day course furnishes a comprehensive introduction to IPC-7092, “Design and Assembly Process Implementation for Embedded Components.” The material presented has been developed to better enable the product designer and manufacturing specialist to have a clear understanding of the principles for embedding components in an organic multilayer circuit board structure. The course will include design guidelines, material selection and termination methodology for embedding active and passive components, including formed and placed resistor, capacitor and inductor elements. Process variations for embedding and interconnecting thinned semiconductor elements within the multilayer PCB will be illustrated with examples of both core type and coreless substrate structures. This course has been prepared specifically for PCB designers, design engineers and those responsible for semiconductor package and electronic product development, assembly processing and manufacturing efficiency. This would include manufacturing and test engineering specialists for the OEM, ODM, EMS and OSAT (outsourced assembly and test) providers. Topics addressed: industry drivers for embedded component technology; economic benefits for embedding components; comparing passive component variations; formed passive component methodology; discrete passive component selection criteria; addressing key factors in planning for ECP; preparation for embedding semiconductors; issues and concerns related to component supply chain; core and coreless embedded component structures; base material selection for the ECP application; embedded component substrate development; land pattern and circuit routing recommendations; component attachment processes; embedded component assembly variations; semiconductor interface variations; qualifying embedded component PCB fabricators.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
 
17: The Basics of PCB Fabrication (101)
Speaker: Paul Cooke, FTG

With ever-decreasing geometries and increased density, today's printed circuit boards (PCBs) are extremely complex. This seminar looks at how a PCB is fabricated and the challenges the fabricator faces to achieve design intent and meet customer and industry standards. The presentation will examine processes needed to form microvias, image microBGAs, plate copper in holes the thickness of a human hair, and select surface finishes needed for very tight pitch components. The half-day seminar will be interactive with the audience to ensure any and all questions related to more in depth PCB fabrication and processes are answered.

Who should attend: PCB Designer/Design Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate

9:00 a.m. - 10:00 a.m.
18: How the IPC Digital Product Model (DPM) Working with IPC Connected Factory Exchange (CFX) Can Improve Product Quality, Performance and Reliability
Speaker: Hemant Shah, Cadence Design Systems

Factory automation (Industry 4.0), IoT and the adoption of IPC Connected Factory Exchange (IPC-CFX / IPC-2591) provide an excellent opportunity to exchange electronically executable data between design houses and their manufacturing partners. Electronic exchange of data utilized through a standard way in a timely manner enables design houses to improve product quality, performance, reliability and cost. This session will talk about how IPC Digital Product Model (IPC-2581), working with IPC Connected Factory Exchange, leverages the benefits derived from adoption of Industry 4.0 in factories. It will provide an update on continued adoption of IPC-Digital Product Model (IPC-DPM / IPC-2581) in the industry, an update on adoption of IPC-Connected Factory Exchange (IPC-CFX/IPC-2591) and where the two standards are going to improve product quality, performance, reliability and cost.

Who should attend: PCB Designer, Design Engineer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator,Test Engineer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. – 6:00 p.m.
EXHBITION HALL OPEN
10:00 a.m. – 2:00 p.m.
EXHIBIT HALL BOOTH BARISTA, Sponsored by Zuken
9:00 a.m. – 11:00 a.m.
19: An Intuitive Approach to Understanding Basic High-speed Layout
Speaker: Keven Coates, Geospace Technologies

What is a wire? At high-speeds, it behaves very differently from what we were taught in college! This is a presentation on high-speed basics that helps make the subject intuitive in a way that’s never been presented before. Learn about how frequency enters the picture, high-speed signal propagation, impedance, noise, and reflections with easy-to-understand animations and analogies to understand this subject on a deeper level.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner

 
20: PCB Layout of Switch Mode Power Supplies
Speaker: Rick Hartley, RHartley Enterprises

When executing PCB layout, we tend to treat digital circuits differently from analog circuits. Each has its own critical requirements. Switch mode power supplies are another wrinkle altogether, and usually need to be treated differently from either analog or digital structures. All switch mode power supplies have four to five circuit loops, all of which are important, but a couple of these loops are downright critical in terms of PCB layout. An improperly designed switch mode supply will often not function as intended, and, in some cases, will not function at all. In contrast, understanding what makes up a switcher circuit and knowing how to take care of the loops during board layout will allow these supplies to operate flawlessly, and with very high efficiency. This two-hour course will outline the difference between switchers and series-regulated power supplies, the different types of switcher circuits (buck, boost, etc.), basic theory of operation of switcher circuits and the impact of the various components, definition and behavior of the five loops, layout to isolate loops from one another and to minimize voltage drop and to control current paths, layout to minimize noise and EMI, effects of paralleling output capacitors, and proper grounding technique.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Intermediate

10:00 a.m. - 12 noon
21: PCB Design Techniques to Improve ESD Robustness
Speaker: Dan Beeker, NXP Semiconductor

Raise the shields, Scotty! Starting with some simple definitions for ESD/EOS, this session describes the important differences in the energy involved and the type of damage that can result. The presentation focuses on PCB design techniques as a means of improving system robustness.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced

11:00 a.m. - 12 noon
22: Multidiscipline Real-Time Team Design
Speakers: Working closely with design team members plays a critical role through all stages of the design process. Today the collaboration between PCB designers and SI/PI engineers is best characterized as “over the wall.” SI/PI engineers often make a copy of the PCB design, analyze it and, by the time they comeback with the recommendations, PCB layout has already moved ahead. Scheduling weekly design review meetings can help bring team members closer, but finding a time/day that works for everyone is always difficult. This means the SI/PI engineers’ intent and PCB design diverge. PCB designers rework some of their work. And this goes on until the design is signed-off. Old, time-consuming, frustrating methodology. This presentation will discuss a new approach and methodology that empowers the PCB designer, eliminates time-consuming rework, and reduces/eliminates unnecessary iterations to ensure all requirements are met. Allow these subject matter experts to engage with the PCB designer without the downtime of attending meetings instead of moving forward with design activities. It also provides a methodology for SI/PI engineers to apply their expertise throughout the PCB design cycle without disrupting the project with formal meetings, while reviewing the PCB designer's work as it is completed.

Who should attend: PCB Designer, Design Engineer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate

 
23: PCB Transmission Line 101
Speaker: Atar Mittal, Sierra Circuits

A PCB transmission line is a type of interconnection used for moving signals from their transmitters to their receivers on a printed circuit board. A PCB transmission line is composed of two conductors: a signal trace and a ground plane. Both remain separate from each other. The volume between the two conductors is usually made of a very low-loss dielectric, called the PCB dielectric. The alternating current that runs on a transmission line has a frequency high enough to take its wave nature into account. It means that at high frequencies, transmission lines need to have a controlled impedance to predict the behavior of the signals. Do not ignore transmission line effects in order to avoid signal reflections, crosstalk, electromagnetic noise and other issues that could severely impact the signal quality and cause errors. At high frequencies, transmission lines need to have a controlled impedance to predict the behavior of the signals and avoid signal reflections, crosstalk, electromagnetic noise, etc., which could damage the signal quality and cause errors. This is the reason you need to know at which speed signals propagate on transmission lines and the time they take to do so. We will give a few equations to calculate signal speed and propagation delay for striplines and microstrips.

Who should attend: PCB Designer, Design Engineer
Target audience: Intermediate
12 noon – 1:00 p.m.
LUNCH on the Exhibit Floor, Sponsored by Sierra Circuits
1:30 p.m. - 3:30 p.m.
24: Power Distribution Made Easy
Speaker: Dan Beeker, NXP Semiconductor

Full power helm! A new way to design your power system, focused on the “plumbing!” A simple EM physics and geometry-based approach to designing power distribution networks on PCBs. From input power connection to the IC die, the simple rules discussed can be used to reduce power supply noise and improve EMC.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
1:30 p.m. - 5:00 p.m.
25: Designing PCBs with HDI Technology
Speaker: Susy Webb, Design Science

With the pitch of the parts getting tighter and the pin count of BGAs going up, there is a need to get as much routing on as few layers as possible, into very dense areas of the board. HDI will help accomplish this, but the technology requires some different setup and thought as to what is needed and how to accomplish it from a design perspective. First, the designer needs to understand the structure of the HDI traces and vias, and what their options and effects are to the cost and electronics involved. The presentation will go into the different possible stackup types and discuss ways to get signals and powers from layer to layer in the board. Then we will move into possible patterns and grids such as via-in-pad, offset or swing vias to maximize fanout and routing opportunities, all the while keeping routing return, power distribution, and layer paired routing in mind. Last, we will talk about the benefits to other parts on the board that HDI can provide, and some information about the unique manufacturing needs of these types of boards.

Who should attend: PCB Designer, Design Engineer, Hardware Engineer
Target audience: Intermediate
 
26: Circuit Grounding to Control Noise and EMI
Speaker: Rick Hartley, RHartley Enterprises

When time-varying (AC) signals travel in the transmission lines of a PCB, state-changing electric and magnetic fields are present. These fields, when not controlled, are the source of noise and EMI. In recent years ICs with very fast rise-time outputs have made problems common, even in circuits clocked at low frequencies. Knowing all the basics of proper grounding will contain and control fields, making noise and EMI issues virtually nonexistent. This 3.5-hour course will focus on the issues PCB designers and engineers need to know to prevent noise, EMI and grounding problems in today’s circuits. We will discuss what is meant by “grounding,” where energy travels in the PCB, location of high- and low-frequency currents, keys to controlling common mode EMI, cables and other radiators, effects of IC style and packaging on overall grounding, impact of connector pin-out, best locations for IO connectors, divided planes and plane islands in the PCB, routing to control noise, best board stackups and filtering of single-ended and differential IO lines.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Intermediate
 
27: PCB Design for High Reliability
Speaker: Paul Cooke, FTG

Designing printed circuit boards (PCB) and assemblies is more difficult than ever due to complexity, component availability, thermal requirements, signal integrity, material selection, layer counts, harsh environments and increased functionality, all required in smaller form factors. We will look at all the elements to successfully design a PCB that can meet all the designers’ requirements and perform to the customer and industry standards, as well as survive in today’s harsh environments. We will look at everything from materials to surface finishes and testing to ensure the product is as robust as possible with a high level of confidence that it has been designed for extended life in the field.

Who should attend: Fabricator Engineer/Operator
Target audience: Beginner, Intermediate
 
28: Establishing an Effective PCB Systems Design Validation Process to Reduce Design Spins and Increase Product Quality
Speaker: David Wiens, Mentor, a Siemens Business

Increasing performance requirements, coupled with a pressure to improve product quality, are driving engineering teams to consider alternatives to their current validation approach. Best-practice design processes validate the digital twin (a model of your design) early and often to minimize re-spins and shorten the overall design cycle. This “shift-left” approach enables design engineers and layout designers to validate within their native environment, minimizing the bottleneck waiting for specialist reviews, and freeing the specialists to resolve the remaining critical issues. This process allows engineering teams to better cope with increasing complexity and focus their efforts on product innovation. This session will cover research on best-practice process strategies, as well as implications of avoiding them. Case studies will show how engineering teams have deployed an “optimal” automated validation process to accelerate sign-off. Analysis technologies that could be deployed within any ECAD flow will be discussed, including multi-board schematic, signal and power integrity, analog/mixed signal, thermal, vibration and manufacturability.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate
 
29: Heat Management for SMD, LED, and Systems 1W to 50W
Speaker: Keven Coates, Geospace Technologies

Do you use power MOSFETs, high power LEDs, power resistors, or hot processors in your design and want to avoid heat-related system failures? This course covers the best options for managing heat cost-effectively and reliably. It gives an overview of PCB design to maximize SMD/LED heat dissipation. It also covers how to choose the right heat sink interface materials, heat sink designs, natural and forced airflow options, as well as heat dissipation simulations (both mechanical and in software). We'll go over helpful tools and break down thermal resistance equations to simple terms. Heat management doesn't have to be scary. Take this class to know your options.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
 
30: Cost-Conscious Test Strategies for Electronic Products
Speaker: Robert Hanson, Americom

This tutorial will focus on the main issues of testing today, which consist of a) disciplines of testing the bare board, b) testing on the production line for minimum ppm defects, c) testing for fault detection/fault isolation on the production line using ICT, boundary scan, flying probe and vision for correcting the processes. Finally, at the system level static and dynamic functional test is performed using embedded firmware, boundary scan and functional test equipment. However, the reliability of the end item is predicated on strategic testing of all items that make up each circuit card, black box, cable, assembly, and the software firmware that defines system performance.

Who should attend: System Designer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, Test Engineer
Target audience: Intermediate
3:30 p.m. - 5:30 p.m.
31: Better Board Buying
Speaker: Greg Papandrew, Better Board Buyers

Want to be a better PCB buyer? Want to employ better board buyers? PCB sales expert Greg Papandrew has the hard-won industry insight you need. This workshop is for procurement staff and managers, company executives and engineers who specify their own boards. Among the topics covered are how to evaluate your current vendor base and new vendors; how to leverage your buying power to get the best price on PCBs; navigating onshore vs. offshore based on order size and technology type; how to identify quality pitfalls; and how to quickly resolve quality issues. All attendees will receive a free copy of PCB Basics, an easy-to-read reference book that is a great tool for anyone in your organization.

Who should attend: Purchasing, Management
Target audience: Beginner, Intermediate
5:00 p.m. – 6:00 p.m.
EVENING RECEPTION on the Exhibit Floor sponsored by Ultra Librarian

Tuesday Sept 10th - FREE SESSIONS

Tuesday, September 10th - Free Sessions
9:00 a.m. – 10:00 a.m.
F1: Last Minute DfM in a Crazy Prototype World
Speaker: Duane Benson, Screaming Circuits
 
F2: Effect of Stimulus Patterns (Even/Odd) on Supply Rail Noise and Resonance in PDN in Parallel Bus Interface
Speaker: Vinod Huddar, Western Digital
10:00 a.m. – 11:00 a.m.
F3: What Every Circuit Board Designer Needs to Know about SI and PI
Speaker: Dr. Eric Bogatin, Teledyne LeCroy
 
F4: Tier 3 Reciprocal BoM Methods Contest Tier 1 Cost Models
Speaker: Joe Fama, TCE Inc.
11:00 a.m. – 12:00 noon
F5: How Leveraging Software-Powered Electronics Manufacturing Facilitates Innovation and Enables Faster Time-to-Market for PCBA
Speaker: Shashank Samala, Tempo Automation
 
F6: Design Considerations for Heavy Copper PCBs
Speaker: Greg Ziraldo, Advanced Assembly
1:00 p.m. – 2:00 p.m.
F7: Unleashing Electronics Design with Additive Manufacturing
Speaker: Ofer Maltiel, Nano Dimension
 
F8: Going Paperless to FAB and Assembly with IPC-2581
Speakers: Stan Keightley Jr., WISE Software Solutions
2:00 p.m. – 3:00 p.m.
F9: An Overview of Glass-Weave Effect for PCB-Based RF and High-Speed Digital Applications
Speaker: John Coonrod, Rogers Corp.
2:00 p.m. – 4:00 p.m.
F10: 21 (and Counting) Most Common Design Errors, Caught by Fabrication, and How to Prevent Them
Speakers: Dave Hoover, TTM Technologies, Ray Fugitt, Downstream Technologies and Mike Tucker, Kinwong Corporation
3:00 p.m. – 4:00 p.m.
F11: Characterization of High-Tg FR-4 Reliability in High-Temperature Application
Speaker: Matthew LaBar, Bay Area Circuits, and Troy Topping, Ph.D.
4:00 p.m. – 5:00 p.m.
F12: Jump-Starting your PCB Design – Getting the Data Upfront (Rules, Stackup)
Speaker: Ed Acheson, Cadenc
4:00 p.m. – 5:00 p.m.
F13: Writing Your Résumé and Marketing Yourself Within Your Company
Speaker: Gary Ferrari, FTG Corp.
5:00 p.m. – 6:00 p.m.
EVENING RECEPTION ON THE EXHIBIT FLOOR sponsored by Ultra Librarian

 

Wednesday Sept 11th

Wednesday, September 11th
8:00 a.m.
Conference Coffee Break, Sponsored by Sierra Circuits
8:30 a.m. – 12 noon
32: PCB Design of Power Distribution and Decoupling
Speaker: Rick Hartley, RHartley Enterprises

Power distribution in PCBs is the foundation around which all things work in the circuit. If this is not designed correctly, the entire circuit is at risk from noise and signal integrity issues, to say nothing of the severely increased possibilities of EMI. Low impedance in the structure, across the harmonic frequency range of a digital circuit, is critical. Subtle layout techniques have a fairly major impact on power bus impedance, inductance in particular. This 3.5-hour course will cover power bus target impedance, inductance of vias, planes and capacitors, mounting inductance of capacitors, energy delivery to IC cores, the “Bandini Mountain,” best mounting of capacitors based on board stackup, the importance of IC pin-out, placement of decoupling in low- and high-layer-count boards, real performance of capacitors (verses myth), how much decoupling, multiple capacitor values, how to minimize anti-resonant peaks, ferrites in the power bus, analog and RF decoupling, the importance of power/ground plane pairs, ultra-thin power and ground plane pairs, and the importance of board stack.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Intermediate
 
33: A Beginner's Guide to Intuitive RF/Microwave PCB design and Prototyping
Speaker: Benjamin Jordan, Altium

RF and microwave elements are becoming more prevalent thanks to market demands that everything must be wireless. Yet for many, RF/microwave elements on the PCB design remain something of a mystery. Some folks even design by formulas, without a completely intuitive understanding of what's going on in those PCB structures. The purpose of this practical workshop is to discuss the most commonly found microwave PCB design elements, with a series of intuitive visual presentations of what's going on. These will be interspersed with practical design and will be using a desktop PCB prototyping mill to create some structures to be measured with a low-cost USB vector network analyzer. The goal will be attendees leave the session with a better internal visualization of what goes on in the PCB, but also an understanding of the following key items: wavelength (EM waves in PCB structures; some useful free calculators and website references to use); why a 1/4 wavelength (and its multiples) is important; how to design PCB microwave transmission lines (CPWG and microstrip); what a 1/4 wave stub is, and when to use and how to design it; PCB antennas: dipole, F, inverted F, etc.; impedances and impedance matching; how to measure prototypes with a low-cost USB VNA; how to mill RF prototypes with a desktop PCB mill; and practical comparisons of base materials (phenolic and FR-4). 

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner
 
34: Part Placement Choices and Consequences
Speaker: Susy Webb, Design Science

There are many ways to place parts on any board, but clearly some ways work better for physics, electrical, and mechanical purposes. If a new board works electrically but won’t interface properly with the rest of its system, it may require costly and time-consuming redesign and retesting. Designers must understand the board, electrical and system needs, as well as typical placement and routing guidelines and consequences of not adhering to them. When they understand the reasoning behind these things, and the affects they have on one another, designers will intuitively know how to make good decisions for their own board designs, and thus avoid problems. In this presentation, we will discuss choosing effective parts, approximate order of overall placement, placement to set up routing, board and system consequences, manufacturability, and more.

Who should attend: PCB Designer, Design Engineer, Hardware Engineer
Target audience: Intermediate
9:00 a.m. - 11:00 a.m.
35: The Mystery of Bypass Capacitors
Speaker: Keven Coates, Geospace Technologies

How do you design a high-speed digital circuit with enough bypass caps in the right area to supply all the peak power demands? You can’t listen to all the expert advice because it seems they can’t even agree! This presentation covers power distribution network basics and shows three approaches with simulation results for each, and some real-world experience and advice on bypassing for high-speed circuits.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
 
36: Electromagnetic Fields for Normal Folks: Show Me the Pictures and Hold the Equations, Please!
Speaker: Dan Beeker, NXP Semiconductor

It’s all about the space! Here we cover basic principles of electromagnetic fields, presented in easy-to-understand language with plenty of diagrams. Discover how understanding EM field behavior allows the design of more robust PCBs with better EMC performance. This is not rocket science, but an easy-to-understand discussion of how to use PCB geometry to control the fields.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
9:00 a.m. - 5:30 p.m.
37: IPC Standards Evolving to Meet Current and Future Requirements
Speaker: Gary Ferrari, FTG Corp.

Our industry is evolving rapidly with newer applications, components, materials, and respective reliability requirements. To this end, IPC has placed standards updates and development on a fast track. New market segments are adopting IPC standards. However, these market segments may require some differences in what the current standards contain. To meet this requirement, IPC developed several addendums to existing standards. These addendums were written by their respective market segment leaders. Market segments such as automotive, medical and space, have participated in this effort. This session will highlight the major changes in the most popular standards and address any associated addendums. This will be an interactive discussion covering the important standards details that affect your current product designs, as well as the new changes mentioned above. Ample time will be allotted for discussion and questions.

Who should attend: PCB Designer, Design Engineer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, Test Engineer
Target audience: Beginner, Intermediate, Advanced
11:00 a.m. – 12 noon
38: CAE for Upfront DfM and Configuration Validation of PCB Plating Process
Speaker: Robrecht Belis, Elsyca

PCB designers can find all kinds of advice, rules of thumb, experience and other guidance to ensure the board designs are good and the layout of the boards on the panels will result in quality products. PCB fabricator engineers use a similar approach to find the best configuration to provide the most uniform plated layer thickness distribution over the panels and inside the holes. Unfortunately, the above may lead to surprises and quality problems on the end product, even for the most experienced users. In this presentation, it is demonstrated how a CAE approach (making use of computer simulations) can be used for a fast evaluation of the expected copper layer thickness distribution and possible mitigation strategies, even before the first panel is manufactured. These mitigation strategies are a combination of improved product design and/or layout of the product on the panel, the use of tooling elements (current robbers and shields) and improved process conditions (imposed currents, plating times, other rack layout).

Who should attend: PCB Designer, Design Engineer, Fabricator Engineer/Operator, Test Engineer
Target audience: Beginner, Intermediate, Advanced
 
39: Integrated Design and Analysis for PCB Designers
Speaker: John Carney, Cadence

Are you concerned about impedance, coupling, return path, insufficient power, or cross talk? Do you or your design teams struggle to analyze your design because your SI experts don’t have any available bandwidth? Are your designs getting complicated enough that rules of thumb no longer cut it? Pushing SI and PI analysis earlier in the design cycle can eliminate a process bottleneck. Giving your PCB designers the ability to analyze impedance, crosstalk, coupling, reflection and DC simulation can be the key to preventing your design teams from facing PI and SI problems when project deadlines are looming at the end of the design timeline. This paper will discuss how to enable the PCB designer to find and fix SI and PI issues. This will enable your experts to focus on signoff, optimization and system simulations.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
12 noon - 1:00 p.m.
LUNCH-N-LEARN, Sponsored by Polar Instruments
1:30 p.m. - 3:30 p.m.
40: Analytic Approach to Project Management of PCB Designs
Speaker: Timothy Lombard, PCBevo

PCB layout is a complex and often fast-moving transformation of a design concept into the real fabrication spec for a prototype. Tracking PCB layout progress can provide powerful insights and inform decisions for meeting new product goals. Often it is difficult to estimate key parameters accurately in advance, and layout starts in an exploratory mode to answer key questions. In addition, simulation or other analysis of the circuit may continue after a netlist has been provided to start layout and defects, or needed improvements are discovered that lead to a design change or ECO before the layout is complete. While modern layout systems are very good at managing the version-to-version change process, they don't do as good a job at tracking design progress and the impact of changes late in the process on work that had been provisionally marked as complete. We will explore methods for tracking not only the evolution of the design in an ideal case – where no changes are made once the netlist is delivered – but also in the more common case where one or more rounds of changes need to be incorporated in a particular board version. Discussion of challenges faced by layout managers, including tracking the evolution of the design, assuming a clean start (no changes to netlist). This is "default evolution," which allows some prediction for completion tracking the impact of a design change on progress to date/working with an engineer to anticipate changes and prioritize efforts either for learning to reduce uncertainty or to minimize effects of likely impending changes. It also allows an accurate estimate of revised schedule (whether or not some buffer was allowed for changes), looking post-delivery at the sequence of changes, the total amount of work (normally more, perhaps 2-3 times what a clean start would have entailed). Implications for a design-layout working relationship, policies, etc. Normally in the context of a single project evaluation of project-level work relationship/project-level impact of changes looking across a set of boards to determine what are patterns to completion, which engineers/boards were outliers in terms of number of severity of changes, again with an eye to relationships between departmental service-level evaluation, design guidelines for the amount of work an early start with changes or frequent design changes can have. Key concepts: How key measures can be tracked as they progress toward 100%. How can data analysis provide early detection and impact reporting should the scope change? How can data analysis justify a new agreement for more time or money? How can one start collecting data on PCB layout progress to analyze?

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate
1:30 p.m. - 2:30 p.m.
41: HDI – High Density Interconnect
Speaker: Harry Kennedy, NCAB Group

What defines an HDI board, standards, design rules, and driving forces for HDI? How do you get started with HDI? This learning module is compiled to help designers, NPI teams and project managers better understand the features in an HDI PCB design. The module will cover the basic use and design considerations for high-density interconnects and will provide guidance on types and constructions for HDI, including predominant industry methodologies and relative costs. The objective of the module is to give designers and other PCB professionals basic guidelines that will allow them to make HDI design decisions based on design constraints that influence manufacturability.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate
1:30 p.m. - 5:00 p.m.
42: Thermal Management Solutions Using PCBs and IMS
Speaker: Mike Tucker, Kinwong Corporation

Thermal management solutions, metal-backed boards, copper-inlay and metal-core boards. As we move into the future, LED applications and power supplies are becoming more prevalent. It is important that designers and program managers understand how material selection, design rules, and performance requirements affect not only the product’s performance, but how these decisions can affect cost. What will you learn: This course will cover topics ranging from material selection and stackup to design rules for copper, blind-via structures, copper-inlay stackup/shapes, solder mask, etc. We will discuss basic cost-related factors as we present each parameter of the thermal management solution. In addition, we will discuss performance and reliability tests based on our experience and testing results. Who will benefit: PCB design engineers, mechanical engineers, PCB layout drafters, PCB buyers, anyone involved in LED and power supply.

Who should attend: PCB Designer, Design Engineer, Hardware Engineer, Fabricator Engineer/Operator, Purchasing
Target audience: Beginner
 
43: RF and Mixed Signal PC Board Design
Speaker: Rick Hartley, RHartley Enterprises

This session is intended for board designers to understand the “things” RF engineers request during PCB layout. (Experienced RF engineers will likely not learn anything new from this course, as the material is mainly geared to board designers.) Due to sensitivity in analog circuits, the keys to full functionality (whether the design is for very high-frequency analog PCBs, mixing RF with digital, or mixing low-frequency analog with digital) are signal integrity and noise control in the design of the printed circuit board. This course will cover differences among analog and digital, circuit changes over time, lumped vs. distributed length lines, reflections/return loss/VSWR, low- and high-frequency current, transmission line behavior, impedance control, microstrip vs. stripline, coplanar waveguide with ground, circuit termination, 1/4 wavelength couplers and filters designed into board copper, layout techniques and strategies, critical routing and circuit isolation, ground plane splitting (when to and when not to), mismatched loads and other discontinuities, signal splitters, tuning transmission lines, power bus decoupling for RF vs. digital circuits and PC board stackups for mixed RF and digital circuits.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Intermediate
 
44: Mentoring Extended PCB Design Techniques
Speaker: Susy Webb, Design Science

Many classes discuss the aspects of PCB design from an electronics or DFM perspective. This class will be about some of the less common tips that seasoned designers develop over the years to help during their design processes. We will discuss practices that will help with routing, such as units, building grid systems, setting up routing channels, and “rough-in” routing. Placement of “like” groups of parts can be done with a step and repeat process that may also work well for routing. Color-coding is used by some designers to be able to see nets, busses and groups clearly. Often boards will need some big changes during the design, or as part of the next revision. We will discuss ways to make changes as efficiently as possible. There will also be a discussion about some of the pros and cons of hand routing and auto routing, and using your software’s automation tools, including constraints, even if you don’t auto route. This can be an interactive presentation, so come share your own techniques that work well for you!.

Who should attend: PCB Designer, Design Engineer
Target audience: Intermediate
2:30 p.m. – 4:30 p.m.
45: Laying Out Analog/Digital Planes
Speaker: Robert Hanson, Americom

This tutorial will discuss the properties behind ground. This tutorial will address the following questions and more: Which should be used for your design: ground, modified or multipoint ground? What causes near-end and far-end crosstalk, and how is it measured and simulated? Why are solid ground planes best? What is intelligent parts placement, and what is its effect on ground return current? Attendees will learn about the concept of moats/floats/drawbridges, how to layout split planes – CMOS/TTL, PECL, analog using different biases, and also controlling crosstalk, characteristic impedance and cost in 4, 6, 8, and 10-layer stackups using the same bias voltage; how to stack printed circuit board layers (e.g. 4, 6, and 10-layer for Zo and crosstalk control; copper fills on signal layers, minimizing warpage; interplane capacitance: material thickness and selection and stackup placement; SIR vs. frequency; software for performing crosstalk; ground bounce tests.

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator
Target audience: Intermediate

Thursday Sept 12th

Thursday, September 12th
8:00 a.m.
Conference Coffee Break, Sponsored by Sierra Circuits
9:00 a.m. – 5:00 p.m.
46: Getting to 32Gb/S: A Tutorial on How to Design Very High-Speed Differential Signals
Speaker: Lee Ritchey, Speeding Edge

This one-day course is intended to cover all the technical issues involved in the design of very high-speed differential pair signal paths. This is a thorough treatment of all the topics to consider to be successful as the speeds of differential pair signal paths increase. 28Gb/S signaling is already being successfully shipped in high-performance servers, routers and switches. When data rates exceed 5Gb/S, there are areas to manage that were not significant issues at lower data rates. Among these are the type of glass weave used in laminates, the surface finish on the copper used for signal layers and the loss characteristics of the laminate itself. Vias and other drilled holes can have a significant effect on signal quality if not properly managed. This course will draw on more than 30 test PCBs built to determine the properties of new laminate systems, as well as to measure the effects of vias, plane crossings and other features that might affect high-speed signals.

Topics include how differential pairs operate; power delivery issues with differential pairs; managing crosstalk in differential pairs; signal degradation sources (a real data path will be modeled and signal speed increased); bandwidth requirements for differential pairs; how skew affects differential pairs; how laminate choices affect skew; managing skew in differential pairs; how laminate choice affects loss; how choice of copper finish affects loss; how processing at fabricators affects loss; routing differential pairs for optimum performance; choosing connectors for high-speed differential pairs; connector pin-out to minimize unwanted crosstalk; how vias affect signal quality; when vias can be ignored; how to prevent vias from degrading signal quality; choosing materials that enable good signal quality without over-specifying; is a low DK (dielectric constant) material necessary for high-speed signaling?; handling high-speed differential signals on twisted pairs; handling high-speed differential pairs on flexible circuits; characteristics of new laminates developed for high-speed signaling; adaptive transceivers; equalizing techniques; simulation of high-speed data paths; and documentation required to ensure boards containing high-speed differential pairs are properly fabricated .

Who should attend: PCB Designer, Design Engineer, System Designer, Hardware Engineer, SI Engineer, Fabrication Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
12 noon - 1:00 p.m.
LUNCH-N-LEARN, Sponsored by Polar Instruments

 

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