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2018 Day-by-Day Conference Program

 

Tuesday Sept 11th

Tuesday, September 11th
8:00 a.m.
Conference Coffee Break, sponsored by Sierra Circuits
8:30 a.m. – 12:00 p.m.
1: PCB Design Strategy for High Density BGA and CSP Components
Speaker: Vern Solberg, Solberg Technical Consulting

The ball grid array and chip-scale package families of components are recognized by many as the best solution for meeting the space restrictions of next-generation portable and handheld electronic products, but companies are also expecting improvements in functionality and performance. Because of the higher terminal density of BGA, fine-pitch BGA and CSP, PCB designers have realized the implementation of proven design rules ensures a positive effect on PCB fabrication yield, assembly process efficiency and end product cost. Furthermore, attendees will be able to explore a number of alternative 2.5D and 3-D semiconductor packaging methodologies, review manufacturers design guidelines and assess alternative assembly process variations for HDI applications. This half-day tutorial will include a study of land pattern geometry options, HDI circuit routing guidelines, as well as the important factors related to specifying base materials and surface finishes that are most compatible with high-volume automated assembly processing. Participants will also have an opportunity to review and discuss JEDEC packaging standards for array configured components, the latest version of the IPC-7094, “Die Size and Flip-Chip BGA Design Standard,” and IPC-7095, “BGA Design Standard,” a document that includes both wide and fine-pitch array packaging methodology. Topics covered: 1. BGA/CSP process technologies and standards; single die package-level assembly variations; 2-D and 3-D multiple die package methodologies; JEDEC standards for BGA and CSP; IPC standards for implementing BGA and CSP. 2. PCB design guidelines for BGA and CSP; component selection and surface area planning; evaluating BGA and CSP terminal variations; land pattern development for array configured components; circuit routing strategies for BGA and CSP. 3. HDI circuit and Microvia design implementation; defining circuit complexity classifications (IPC-2226); analysis and consideration when estimating circuit density; benefits for implementing blind and buried microvias; guidelines for stacked, staggered and in-land microvias. 4. Specifying PCB base material, surface finish and coatings; reviewing established standards for circuit substrate materials; studying alternative high-performance material variations; choosing solder-compatible surface finishes for HDI circuits; specifying suitable solder mask coatings for the PCB. 5. Preparation for high-volume assembly processing; system requirements for BGA and CSP device placement; basic features needed for SMT assembly processing; palletizing to maximize assembly process efficiency; solder stencil development and solder alloy variations.

Who should attend: PCB Designer, System Designer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, Test Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
9:00 a.m. – 11:00 a.m.
2: Layout of Switch Mode Power Supplies
Speaker: Rick Hartley, RHartley Enterprises

When executing PCB layout, we tend to treat digital circuits differently from analog circuits. Each has its own critical requirements. Switch mode power supplies are another wrinkle altogether and usually need to be treated differently from either analog or digital structures. All switch mode power supplies have four to five circuit loops, all of which are important, but a couple of these loops are downright critical in terms of PCB layout. An improperly designed switch mode supply often will not function as intended, and in some cases, not at all. In contrast, understanding what makes up a switcher circuit and knowing how to take care of the loops during PCB layout will allow these supplies to operate flawlessly, and with very high efficiency.

This course will outline the difference between switchers and series-regulated supplies, the different types of switcher circuits (buck, boost, etc.), basic theory of operation of switcher circuits and the impact of the various components, definition and behavior of the five loops, layout to isolate loops from one another to minimize voltage drop and to control current paths, layout to minimize noise and EMI, effect of paralleling output capacitors and proper grounding technique.

Who should attend: PCB Designer, Circuit/Hardware Engineer, SI Engineer, System Engineer
Course rating (Beginner, Intermediate, Advanced): Intermediate
 
3: Power Distribution Made Easy
Speaker: Daniel Beeker, NXP Semiconductor

This presentation will present a simple EM physics and geometry-based approach to designing power distribution networks on PCBs. From input power connection to the IC die, the simple rules discussed can be used to reduce power supply noise and improve EMC.

Who should attend: PCB Designers, System Designers, Hardware Engineers, SI Engineers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
9:00 a.m. – 5:00 p.m.
4: The Basics of PCB Design
Speakers: Susy Webb, Fairfield Industries

Technical sessions at conferences often emphasize the latest techniques and technologies, but those classes are often too in-depth for a novice designer, and don’t speak to the questions from the engineers who need to design their own boards. This class features an overview of the entire process of designing a board, from start to finish. We will begin with creating manufacturable footprints that meet the IPC specs. Then we will address some common placement techniques like floor planning, color coding, flow, orientation, and placement to set up routing. We will follow that with a discussion of planes and stackups and how to configure them to get the best results for parts and signals. Next, we move on to some fanout and routing techniques that are helpful for completing the design connections to meet the number one design rule: good electrical performance. We will complete the process by discussing some manufacturability concerns that can be affected by the way the board is designed, some finishing issues, and sending out good documentation that the manufacturers can easily understand and use.

Who should attend: PCB Designer
Course rating (Beginner, Intermediate, Advanced): Beginner
 
5: What's New in the IPC Design Standards, and How to Use Them
Speaker: Gary Ferrari, FTG Circuits

Designers are under pressure to not only lay out a circuit board to meet functional requirements, but produce a cost-effective design that meets the requirements of fabrication, assembly, test, and field service. As a result, designers must keep up with the latest changes/additions to the industry standards they must use. IPC has shortened the development cycle for many of its standards. This session will identify a minimum set of standards that the designer should be familiar with. Highlighted will be recent important changes to the most used design, materials, fabrication, assembly and test standards. The changes are significant, and affect all classes of products.

Attendees will learn recommended minimum standard set for designers, standards that affect the design of printed boards, and design changes that affect manufacture and reliability of a product.

Who should attend: PCB Designer, Electrical Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
 
6: PCB Stackup Design and Materials Selection
Speaker: Bill Hargin, Nanya

The objective of this tutorial is to guide design teams through the process of evaluating and selecting the right laminate for a design, creating PCB stackups that meet the requirements of complex, multilayer boards that work right the first time, within budget, and with reproducible results across multiple fabricators. The course will go into detail on tradeoffs between loss and cost, including dielectric loss, resistive loss, surface roughness, as well as glass-weave skew. After attending this course, students will be knowledgeable of PCB laminate tradeoffs, the laminate-materials market, and the process of troubleshooting problematic stackup designs. Attendees will also be exposed to cost-effective strategies for controlling loss and glass-weave skew.

Who should attend: PCB Designer, System Designer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator, Other
Course rating (Beginner, Intermediate, Advanced): Beginner, Beginner, Intermediate, Advanced
 
7: Troubleshooting and Defect Resolution of SMT Assembly Processes
Speaker: Jim Hall and Phil Zarrow, ITM Consulting

We don’t assemble electronics in a perfect world. Defects happen. This course examines failures and root cause analysis of PCBA defects, starting with a clear definition of the generic types of defects and their impact, such as non-function, reduced reliability, etc. Detection and determination methodologies and procedures will be discussed. Attributes of specific processes and equipment centers, as well as materials that can contribute to defect generation are identified. Specific defects are then analyzed using these background methodologies: type of defect and impacts, detection methods, possible contributing causes, etc. Finally, general strategies and guidelines for preventing defects will be presented. This seminar is for anyone involved in directing, developing, managing and/or executing failure and root cause analysis and defect resolution, including managers, engineers and others in manufacturing, quality and design.

Who should attend: Hardware Engineer, Assembly Engineers/Operator, Test Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
11:00 a.m. – 12:00 p.m.
8: Managing Your Impedance, Coupling and Return Paths in Design and Avoid Unnecessary Iterations with SI/PI Engineers
Speaker: Dennis Nagle, Cadence Design Systems

Are you fixing high-speed issues on your design by iterating with your SI/PI engineers? There is a better way. This talk will describe how PCB designers can screen their designs and identify issues that can avoid impedance mismatch, crosstalk and return path issues before SI/PI analysis.

Who should attend: PCB Designer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
 
9: Evaluating an Appropriate Power Plane through Power Integrity Simulation
Speaker: Richard Villamor Legaspino, Analog Devices

Most automatic test equipment (ATE) final test boards have analog and digital devices. These devices may be operation amplifier (OP-Amp IC), transistors and memory ICs, which require an appropriate power plane PCB design to connect from voltage source to the load devices. The power plane layout must be carefully designed to prevent power integrity issues such as current-resistance (IR) drop, plane current density, power plane density and power plane impedance. The other way to validate these issues is through power integrity simulation. Simulation can be performed at the pre- or post-layout design stage to prevent any respins of the board. In this presentation, the speaker used the Power-DC and Optimize-PI simulation tool to evaluate the appropriate power plane topology. To measure the IR drop, plane current density, power plane density and power plane impedance of the power plane layout.

Who should attend: PCB Designer, SI Engineer, Assembly Engineer/Operator
Course rating (Beginner, Intermediate, Advanced): Intermediate
 
10: PCB Library Development and Management – A Treatise
Speaker: Vijayakumar David, Tessolve Semiconductor

PCB library, the fundamental block of PCB design, shall adhere to global standards such as IPC to ensure quality. Library parts need to be validated for graphical, logical rules and footprint attributes before release. Appropriate pin grouping, pin type, and multi-part shall be a part of symbol creation. Creating test schematic for symbol, version control, maintaining history, role-based access control, reusability, classification, alternate symbol/footprint, lifecycle status, internal part number, RoHS compliance, and automotive/military compliance are essential requirements. Information about footprints that are associated to padstacks is required before updating a padstack. Creating specific padstacks for BGAs meeting DfM according to pitch saves cost. SMD or NSMD padstacks for BGA, oblong pads for tight pitch PTH parts, pads for specific AWG, half PTH vias, paste-in-hole technology, supported mounting holes, pemnuts, holes for screw numbers, solder mask dam and resist, optimal rules definition for test points placement for flying probe tester and courtyard are some of considerations. Coding specific parts as preferred for a scope helps limit the designer using specific parts only for the scope. Updating specific attribute for multiple parts, team design option, symbol in sync with footprint, parts update alert to designer, and scheduling library distribution across different time zones are the requirements to be addressed. Associating datasheet to a part helps designers review the relevant specification document used for part build. Creating footprints with the right IPC-7351 density level facilitates effective real estate usage. Part of schematic or layout created as block and hierarchical split symbols can be a library part. Assigning specific property value on the discrete parts helps the designer with the task of auto-generation of SI DML models. Preference of SMT over TH components, appropriate termination for backdrilling, considerations for edge mount SMA, CQFP, SMP, pin receptacles selection for ATE boards, datasheet recommendations, slot angle definition in EDA tool and importing 3D models are to be promptly implemented. Automating the library creation process and QA will ensure quality and reduce cycle time. Maintaining a centralized library across multiple locations globally poses a challenge. Parts created need to be replicated immediately to all servers located globally and across the firewall too. Deploying toolsets for immediate replication of parts after release across the globe will reduce cycle time, and having any modified parts available dynamically ensures quality and brings the products on time to market. Effective parts search in the library database is a key requirement for quick retrieval and reuse. Implementing IPC-7351, IPC-7251 standards for footprint and padstack naming conventions adds intelligence for storage and retrieval. Adding specific part properties in addition to those reflected in BOM will help locate the exact part required. Deploying process tools meeting QMS requirements will help automate the library part requests, fill creation and QA checklists, update part status live, etc., ensuring quality process. This talk focuses on the challenges and requirements in PCB library development and management and how these can be effectively addressed.

Who should attend: PCB Designer
Course rating (Beginner, Intermediate, Advanced): Intermediate
12:00 noon – 1:00 p.m.
LUNCH-N-LEARN, Sponsored by Streamline Circuits
(Tuesday Conference attendees and speakers only)
1:00 p.m. – 3:00 p.m.
11: Power Integrity & Decoupling Primer for PCB Designers
Speaker: Ralf Bruening, Zuken

The evolving requirements of new electronic applications in various markets (e.g., automotive, communication, IoT) are forcing engineers to an ongoing improvement of their design processes. The overall performance and the EMC behavior of such electronic systems are determined not only by the design of the circuitry, layout geometry and the IOs, but more these days by the power distribution networks (PDNs). Strict reliability requirements and lack of real estate on such complex systems often prevent first order power integrity countermeasures from the past (e.g., sprinkling the board with 100nF caps). Today’s supply voltage decrease with every new silicon generation is contributing to the problem domain in the same amount as the common goal of reducing power consumption of electronic systems does. This and the resulting shrinking noise margins for new ICs define increasing demands for the quality and stability of power supply systems. Hence, tighter requirements and constraints from silicon 7vendors are defined for the power supply the PCB designers have to follow – in conjunction with tougher decoupling schemes. In this session requirements and the basic of PCB power distribution systems are explained. Issues like plate capacitance, loop inductances and cavity resonance are explained without deep math. Side effects to the signal integrity and EMC domains are shown using illustrated practical examples. Guidelines for a first order covering and resolving power integrity issues are given regardless of the used PCB-design and ECAD process. The how and why of decoupling will be illustrated covering in detail the role of bypass capacitor. Power integrity simulation capabilities will be explained and demonstrated in a generic vendor-neutral manner as a potential problem-solving approach, together with silicon vendor support documents (i.e., constraint and spreadsheet tools) addressing power integrity issues as an essential part of a state-of-the-art PCB design process. Examples from various industries (e.g., automotive) will complement the session with excerpts from practical application experience.

Who should attend: PCB Designer, System Designer, Hardware Engineer, SI Engineer, Test Engine
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
1:00 p.m. – 3:00 p.m.
12: Laying Out Analog/Digital Planes
Speaker: Robert Hanson, Americon

This tutorial will discuss the properties behind ground. This tutorial will address the following questions and more: Which should be used for your design – ground, modified or multipoint ground? What causes near-end and far-end crosstalk, and how is it measured and simulated? Why are solid ground planes best? What is intelligent parts placement, and what is its effect on ground return current? Attendees will learn about the concept of moats/floats/drawbridges, how to layout split planes – CMOS/TTL, PECL, and analog using different biases and also controlling crosstalk, characteristic impedance and cost in 4, 6, 8, and 10-layer stackups using the same bias voltage; how to stack printed circuit board layers (e.g. 4, 6, and 10-layer for Zo and crosstalk control; copper fills on signal layers, minimizing warpage; interplane capacitance: material thickness and selection and stackup placement; SIR vs frequency; software for performing crosstalk; ground bounce tests.

Who should attend: PCB Designer, System Designer, Hardware Engineer, SI Engineer
Course rating (Beginner, Intermediate, Advanced): Intermediate
1:00 p.m. – 4:30 p.m.
13: Effective PCB Design: Techniques to Improve Performance
Speaker: Daniel Beeker, NXP Semiconductor

As IC geometries continue to shrink and switching speeds increase, designing electromagnetic systems and printed circuit boards to meet the required signal integrity and EMC specifications has become even more challenging. A new design methodology is required. Specifically, the utilization of an electromagnetic physics-based design methodology to control the field energy in your design will be discussed. This training module will walk through the development process and provide you with guidelines for building successful, cost-effective printed circuit boards.

Who should attend: PCB Designer, System Designer, Hardware Engineer, SI Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
 
14: Circuit Grounding to Control Noise and EMI
Rick Hartley, RHartley Enterprises

When a time-varying (AC) current flows, state-changing electric and magnetic fields are present. These fields, when not controlled, are the source of noise and EMI. In recent years, ICs with very fast rise-time outputs have made problems common, even in circuits clocked at low frequencies. Knowing all the basics of proper grounding can contain and control stray fields, making noise and EMI issues virtually nonexistent.

This course will cover the concept of “ground,” location of fields in the PCB, when is a circuit a waveguide, where high- and low-frequency currents flow, keys to controlling common mode EMI, cables and other radiators, source control of EMI, effects of IC style and packaging, impact of connector pin-out, effect of component positions on EMI, planes and plane islands in the PCB (to split or not to split ground), routing to control noise, routing and the IO structure, board stack-up, I/O filtering and blocking for single-ended and differential lines.

Who should attend: PCB Designer, Circuit/Hardware Engineer, SI Engineer, System Engineer
Course rating (Beginner, Intermediate, Advanced): Intermediate
3:00 p.m. – 4:00 p.m.
15: Thermal Integrity within an Electrical Design Flow
Speaker: James DeLap, Steven G. Pytel Jr. and Mehdi Abarham, Ansys

Modern design requirements necessitate a workflow that allows for free-flowing information and iterations between electrical, thermal, and mechanical design teams. This workshop will explore new simulation tools that enable electrical and thermal co-design and optimization, as well as showcasing best practices for dealing with electrical and mechanical CAD (ECAD and MCAD) files. The workshop targets electrical engineers providing them an overview of basic thermal dynamics, heat transfer modes, power delivery/consumption optimization in ECAD/MCAD while keeping the focus on how to identify problematic designs early, thereby creating a collaborative working environment with mechanical engineers.

Who should attend: PCB Designer, System Designer, Hardware Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
3:00 p.m. – 5:00 p.m.
16: How to Fight Magnetic Noise Gremlins
Speaker: Keven Coates, Geospace

Flexible printed circuits (FPC) are not new. Yet, FPC is a growing segment and presents some new design and manufacturing challenges. For example, FPCs require new and different manufacturing checks compared to a traditional rigid PCB. These new DfM checks can improve design quality and manufacturing yields. This session will cover the FPC design process and the manufacturing checks that can improve your design and its manufacturability.

Who should attend: PCB Designers
Course rating (Beginner, Intermediate, Advanced): Intermediate

Wednesday Sept 12th

Wednesday, September 12th
8:00 a.m.
Conference Coffee Break, Sponsored by Sierra Circuits
8:30 a.m. – 12:00 p.m.
17: The Complexities of Fine Pitch BGA Design
Speaker: Susy Webb, Fairfield Industries

Designing with BGAs is much more challenging than in the past! The ball pitches are going down, and the total pin counts and package size are going up, making everything more complex. With those changes, the signal integrity and EMI issues become more profound; the fanout and routing are much more challenging, and the power connections more difficult. Add to that the manufacturing concerns that have surfaced from small pad openings and tiny capacitors, and the designer has to face some real complex issues. In this presentation, we will discuss all of those things and more, including choosing effective BGAs, placement for components and caps, grid systems for parts and routing, through-hole and microvia fanout possibilities, and some manufacturing issues unique to these kinds of designs. This class has a lot of illustrations and examples!

Who should attend: PCB designer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
9:00 a.m. – 10:00 a.m.
18: PCB Reverse Engineering Countermeasures
Speaker: Jeremy Hong, Hongs Electronics

Designing circuits and laying out a printed circuit board (PCB) can be a complicated and intensive process. Design engineers use many shortcuts and tricks to cut costs and time of development. As it turns out, many of these shortcuts and tricks can lead to security flaws in a product. Working on both sides, design and reverse engineering, it has been found that implementing security and countermeasures on PCBs are the last priority for design engineers – and sometimes totally ignored. This is apparent in the design of IoT (Internet of things) devices. This presentation points out some fundamental aspects of the hardware design engineering process that can lead to hardware vulnerabilities.

Who should attend: PCB Designer, System Designer, Hardware Engineer, Test Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
9:00 a.m. – 11:00 a.m.
19: Multi-Board Design: Castellation, Connection, SI, Alignment
Speaker: Ben Jordan, Altium

Aesthetics, ergonomics and industrial form are paramount design objectives, as new products must appeal to attention-starved consumer audiences. Intelligent people increasingly crave intelligent products. The desire to maximize production efficiency by consolidating all the electronics onto one board is at odds with higher mechanical design priorities. Add to that the desire markets inherently develop for configurations and optional extras, and it’s hard to avoid a multi-board design approach. This technical session presents practical approaches to multi-board system-level PCB design, including partition boundaries, subcircuit relocation, interconnect methods, panels and layer stacks, and mechanical integration with enclosure design. We will also cover potential disaster areas and ways to avoid pitfalls, how to effectively manage connectivity, and improve manufacturing outputs for unambiguous fabrication and assembly. Specific topics discussed will be multiboard methodologies overview; partitioning; connectors for board to board; castellated module design approach for IPC-610G quality compliance; multiboard signal and power integrity issues; module form factor overview pros and cons; connectivity management and signal probing; 3-D mechanical integration and assembly management. Methods presented in this workshop are extensible and applicable to any toolset or workflow.

Who should attend: PCB Designer, System Designer, Hardware Engineer, SI Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
 
20: An Intuitive Approach to Understanding Basic High-speed Layout
Speaker: Keven Coates, Geospace

What is a wire? At high speeds, it behaves very differently from what we were taught in college! This is a presentation on high-speed basics that helps make the subject intuitive in a way that’s never been presented before. Learn about how frequency enters the picture, high-speed signal propagation, impedance, noise, and reflections with easy-to-understand animations and analogies to understand this subject on a deeper level.

Who should attend: PCB Designer, System Designer, Hardware Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner

 
21: A Beginner's Introduction to PCB Trace Impedance
Speaker: Ken Taylor, Polar Instruments

What is impedance anyway, what causes it, why does it matter, and what happens if we get it wrong? This entry-level presentation describes the component properties of a PCB trace (a transmission line) that come together to determine the impedance. Maybe surprisingly, impedance is experienced in various other forms every day, probably every minute of every day. Most people never thought of it that way. This presentation begins by briefly identifying and acknowledging those experiences, and relates them to the electrical transmission line and its component parts and their characteristics. Next, it looks at the transmitted signal as it progresses from the signal source into the line, as it propagates along the line, and what happens when it eventually reaches the end of the line – depending on how the line is terminated: open/short/matched/mismatched. The mathematics will be kept simple, nothing worse than x = a.y or similar and, of course, the good old square root. A brief review of frequency-dependent problems of dielectric loss (signal energy lost to the line’s surrounding environment) and copper loss (signal energy lost to the copper conductor) might be included.

Who should attend: Fabricator Engineer/Operator, Assembly Engineer/Operator, Other
Course rating (Beginner, Intermediate, Advanced): Beginner
9:00 a.m. – 5:00 p.m.
22: Cost Reduction through Design for Manufacturing and Assembly
Speaker: Gary Ferrari, FTG Circuits

Technologies such as lead-free, small pitch BGAs, microvias, embedded passives, controlled impedance, and EMI present manufacturing challenges that must be addressed by today’s designers, not to mention increased costs. It is easy to blame escalating costs on these technologies. Much of the blame may be attributed to a lack of understanding of the manufacturability rules associated with these technologies, however. Designers should be designing for the most cost-effective product without sacrificing performance.

Cost reduction, by design, forms the fundamental building blocks for this session. This session will be divided between lectures and interactive discussion groups. These groups will explore, under guidance, material issues for lead and lead-free environments, high performance, HDI, assembly, and surface finishes for various environments. There will be ample time allocated to look at individual challenges faced by the attendees.

Attendees will gain a clear understanding of overall DfM issues, cost drivers, how to apply DfM concepts to specific designs, and the notes that should be placed on fabrication drawings.

Who should attend: PCB Designer, Electrical Engineer
Course rating (Beginner, Intermediate, Advanced): Intermediate, Advanced

 
23: The Complete Guide to Understanding Transmission Lines
Speaker: Robert Hanson, Americon

Fundamentals • Frequency, time, and distance • Lumped versus distributed systems • EM fields • Geometry, C, L, and Zo interrelationships • C&L resonance transmission line characteristics • The quality factor, Q, and why lumped circuits can ring and cause EMI • Infinite uniform transmission line • Effects of source and load impedance • Special transmission line cases • Determining line impedance and propagation delay using TDR and VNA • Skin/proximity effect and dielectric loss • The capacitive load: Zo and propagation delay • Matching Zo with trace alterations (neck-downs): minimizing the C load • 90°, 45° bends: are they concerns? • Characteristics of T lines: coax, pair, micro strip, buried micro strip, stripline and differential: asymmetric, dual, edge.

Who should attend: PCB Designer, System Designer, Hardware Engineer, SI Engineer
Course rating (Beginner, Intermediate, Advanced): Intermediate

10:00 a.m. – 6:00 p.m.
EXHBITION FLOOR OPEN
10:00 a.m. – 2:00 p.m.
EXHIBIT HALL BOOTH BARISTA, Sponsored by Zuken
11:00 a.m. – 12:00 p.m.
24: iPhone X – Steve Jobs' iPhone
Speaker: Bill Cardoso, Creative Electron

It’s been 10 years since Steve Jobs introduced the iPhone to the world. Much has happened since then. Over this past decade, the iPhone became a reference design, and the object of desire of a legion of fans who wait anxiously for every launch of the Cupertino company. Undoubtedly, the most advanced iPhone on the market today, the iPhone X is a technology marvel. The double-stacked boards, dual battery, and a face recognition sensor bring the iPhone X to a whole different level. In this presentation, we’ll explore these technological advances during a live teardown of the iPhone X. The teardown will be followed by detailed coverage of the technical details of critical parts of the device. This live teardown will be accompanied by x-ray and CT images of the iPhone X, so the audience will get unprecedented insights on what makes this iPhone tick. More important, we will explore the assembly process utilized to put the iPhone X together. This presentation is targeted at a wide technical audience looking for a better understanding on how advanced consumer electronics are designed and assembled.

Who should attend: System Designer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, Test Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner

11:00 a.m. - 12 p.m.
25: Continuing Test Point Management throughout a PCB Design Flow
Speaker: Mark Laing, Mentor

At PCB West 2017 I presented how design for test (DfT) needed to become proactive in the PCB design flow. This paper focused on starting DfT analysis as part of the schematic capture phase and not leaving it until late in the layout phase. This presentation will continue this theme, and discuss how PCB layout can further enable improvements in testability and DfT, with ongoing test point management as the next logical step from schematic capture. Existing layouts will be reviewed for testability coverage to find ways they can also be improved in subsequent design revisions.

Who should attend: PCB Designer, Fabricator Engineer/Operator, Assembly Engineer/Operator, Test Engineer
Course rating (Beginner, Intermediate, Advanced): Intermediate

 
26: Clock Jitter Behavior on Different PCB Layout Approach
Speaker: Marcus Miguel Villaflores Vicedo, Analog Devices

Clock signal in a PCB spectrum experiences degradation in the form of clock jitters, broadly known as timing deviation. Jitters limit the maximum SNR that can be achieved, especially in the case of ADC devices. Inherent system properties, such as length of the traces and the frequency of operation, contribute to the timing deviation on the signal. PCB design implementation techniques should be evaluated to determine the effective method to reduce clock jitter. Isolating the jitter aggravators calls for eight unique case setups representing the hypothetical stimulus of noise. These setups were derived from the variable matrix: length of trace, guard shielding, and layer-transposition in the design. This talk only supports deterministic jitter (dJ) analysis; any random Gaussian jitter (rJ) that exists on the real-world setups was disregarded. Each case was subjected to simulation, mapping the phase difference graph. Scattering parameters were also plotted to evaluate each setup’s noise performances. Results support the profound effect of trace lengths in the phase difference in each case. Cases subjected to the trace lengths of both extremes give a nonlinear variation, but with relative degree separation in which longer lengths contribute more jitter to the signal. This concludes the rationale of increasing the proximity for T(x) and R(x) lines in clock signal lines. Phase difference on each group of lengths shows consistency, solidifying the matched length effect. Return loss slightly differs between cases of same length and different topology. Hence, different best-design topology does not give drastic advancement or deterioration to the clock performance in comparison within each other. Same goes with insertion loss performance, showing slightly varying results on each grouped trace lengths. This goes to show performance was almost consistent on all types of best layout practices, and only the trace lengths contribute highly to clock jitter.

Who should attend: Who should attend: PCB Designers
Course rating (Beginner, Intermediate, Advanced): Intermediate

 
27: ECAD-MCAD Co-design for a Competitive Advantage
Speaker: Craig Armenti, Mentor

Many design teams struggle to reduce product development schedules and improve time-to-market. In a recent survey, the need to improve time-to-market was identified as a primary business objective, ahead of the need to reduce product cost and improve product quality. Asked about initiatives to accelerate time-to-market, the leading response was to improve communication and collaboration across engineering. If you were to push down further into a methodology to implement this initiative, you would find that improving ECAD-MCAD collaboration not only reduces product development time, thereby improving time-to-market, it also provides a sustainable competitive advantage for your design team. During this session we will discuss how an efficient ECAD-MCAD co-design process can be an enabler for design teams to eliminate costly electro-mechanical issues during new product development. We will look at the innovative solutions available in the latest generation of software technology and how they can help your team obtain a sustainable competitive advantage. Recommended best practices and a summary of the benefits associated with an optimized ECAD-MCAD collaboration process will be reviewed and discussed.

Who should attend: PCB Designer, Other
Course rating (Beginner, Intermediate, Advanced): Beginner

12:00 p.m. – 1:00 p.m.
LUNCH on the Exhibit Floor, Sponsored by Sierra Circuits
1:00 p.m. – 3:00 p.m.
28: Thermal Design Considerations for SMD PCBs
Speaker: Keven Coates, Geospace

By now everyone has seen those nice aluminum core PCBs that dissipate heat fantastically, but what do you do when all you have to work with is FR4 and SMD components? How do you keep those MOSFETs and faster processors cool? How are semiconductor packages designed to dissipate heat? What’s the best way to utilize that? This class will cover understanding thermal resistance, how airflow affects things, good design goals, estimating junction temperature, and how to pick the right components to minimize the temperature of your design and therefore maximize reliability.

Who should attend: PCB Designer, System Designer, Hardware Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate

 
29: Signal Attenuation in Very High Speed Circuits
Speaker: Rick Hartley, RHartley Enterprises

In all high-speed/high-frequency circuits, signal integrity is dependent on a number of variables, all of which accumulate to impact the noise budget of the circuit. With very high-speed circuits, an even larger number of issues come into play, and all the effects are more extreme. Some problems are driven by design deficiencies, some by the physical structure and design of the ICs, and still more are driven by the PCB's copper style and base material parameters.

This course will outline all the effects impacting signal integrity at very high-speeds and will detail such items as via stubs, jitter, inter-symbol interference, impact of copper style on skin effect, loss tangent, impact of layer change during routing and other major signal integrity concerns, as well as the impact some of these items have on timing and the Y-axis attenuation of signal eyes. Also discussed will be solutions to these issues, including some excellent high-speed base materials.

Who should attend: Circuit/Hardware Engineer, SI Engineer, PCB Designer, System Engineer
Course rating (Beginner, Intermediate, Advanced): Intermediate, Advanced

1:00 p.m. – 4:30 p.m.
30: HDI Routing Solutions
Speakers: Susy Webb, Fairfield Industries

With the pitch of parts getting smaller and pin count getting larger, there is a need to get as much routing as possible into very small areas of the PCB. HDI will help accomplish this, but the technology requires some different setup and thought as to what is needed. One has to decide on design priorities, complexity needed, cost required or allowed, the type and size of vias, best via patterns to use, and how signals, power and ground will move from one layer to another. Additionally, the layer structure, impedance, signal return, and layer paired routing all must be considered for signal integrity and EMI control, and a general understanding of manufacturability is needed. We will discuss all those things, the electronics involved, different ways to accomplish the routing, and offer many examples and pictures of how to work with them to reach our goals.

Who should attend: PCB Designer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced

 
31: The Basics of PCB Fabrication (101)
Speaker: Paul Cooke, FTG Circuits

With ever-decreasing geometries and increased density, today’s PCBs are extremely complex. This seminar looks at how a PCB is fabricated, and the challenges the fabricator faces to achieve the design intent and meet the customer and industry standards. We will examine the processes needed to form microvias, image μBGAs, plate copper in holes the thickness of a human hair, and select surface finishes needed for very fine-pitch components. The half-day seminar will be interactive to ensure all questions related to PCB fabrication are answered.

Who should attend: PCB Designer, Fabricator Engineer/Operator, Assembly Engineer/Operator, Test Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner
3:00 p.m. - 5:00 p.m.
32: Differential Pair Routing for SI Control
Speaker: Rick Hartley, RHartley Enterprises

Differential pairs have been used in PCBs for years to carry high-speed serial and high-speed parallel data, in a variety of bus formats. Many board designers and engineers believe the rules for differential pairs are the same in a PC board as they are in a cable or a twisted pair of wires. This is not the case!

This course will cover the advantages of differential pairs vs, single-ended lines, which differential pair format gives the best impedance control, what is the right spacing between the lines of a pair, crosstalk between differential pairs, what’s important in differential pair routing, how much skew (line length mismatch) is really acceptable, the impact of material type and the impact of vias on signal integrity and EMI.

Who should attend: Circuit/Hardware Engineer, SI Engineer, PCB Designer, System Engineer
Course rating (Beginner, Intermediate, Advanced): Intermediate
 
33: Evaluating the VIA Transition through TDR Simulation
Speaker: Richard Villamor Legaspino, Analog Devices

As PCBs become dense, routing high-speed digital (HSD) traces in a single layer have become complicated. Now most of the layout designs use at least two layers for routing these kinds of signals (RF and HSD). The speaker looks at the effects of having stubs in designs, and further improving it by removing the stubs and controlling the vertical interconnect access (VIA) using a 50 Ohm coaxial approach. Trace-to-vertical interconnect access (VIA) transition has been a common issue in high-speed digital PCB designs and applications. The speaker looks at the effects of having stubs in designs, and further improving it by removing the stubs and controlling the VIA using a 50 Ohm coaxial approach. The speaker explores the five different VIA transitions and the effects of each specific method applied to it using EMPro (electro-magnetic professional) FDTD (finite difference time domain) TDR (time domain reflectometry) simulation in correlation to an actual design. The speaker used a 3-D simulation tool, which is EMPro, using FDTD Solver for TDR and FEM (finite element method) for S-parameter analysis. The speaker fabricated a simple circuit board design using a micro-strip single-ended trace to via transition for correlation.

Who should attend: PCB Designer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
Wednesday, September 13th - FREE SESSIONS
9:00 a.m. – 10:00 a.m.
F1: Routing & Termination for Control of Signal Integrity
Speaker: Rick Hartley, RHartley Enterprises

IC output rise time contributes more heavily to loss of signal quality than the clock frequency of the circuit. Since most ICs today have rise and fall times under 1.0 nanosecond, many engineers and printed circuit designers find themselves fighting signal integrity problems in circuits being clocked in the low to mid tens of megahertz. Traces on circuit boards with rapid rise and fall times are referred to as high-speed transmission lines. The single greatest contributor to signal integrity issues is the lack of proper routing of lines, lack of or poor control of impedance and the lack of proper termination.

This course will focus on the issues PCB designers and engineers need to know when designing with today’s “high-speed” components. Topics include: At what length a line is high speed, line length’s effect on signal integrity when proper routing is not implemented, understanding and controlling line impedance, PCB material impact on impedance, long “Ts” in lines, routing schemes that work, when to terminate a line, proper termination of the line, when termination is not needed and board stack-up.

Who should attend: Circuit/Hardware Engineer, SI Engineer, PCB Designer, System Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
 
F2: HDI: High Density Interconnect
Speaker: Chris Nuttall, NCAB Group

How do I get started with HDI? This session explains what defines an HDI board, standards, design rules, and driving forces for HDI.

Who should attend: PCB Designer, System Designer, Hardware Engineer, Test Engineer, Other
Course rating (Beginner, Intermediate, Advanced): Intermediate, Advanced
10:00 a.m. – 11:00 a.m.
F3: AI and Machine Learning Disrupting the Manufacturing of Your Products
Speaker: Albert Yanez, AsteelFlash

In manufacturing, we work systematically at ways to save time while maintaining the highest yields. This has been evident over the past 50 years, as methodologies were born that would help streamline operations and indoctrinate staff. These have helped form today’s best practices, followed in every modern manufacturing company globally. These processes and systems can be seen in the assembly line, such as TQM (Total Quality Management), Six Sigma and Lean. We also know future products will be even more design savvy, with intricate and custom fabrication methods and materials. From diagnostics equipment through to the most advanced automotive systems, we could see what was needed to outpace, while providing no decrease in quality. Then, we considered the challenges our clients face forecasting, dealing with supply-chain concerns and distributing key materials as end-products require. We needed a manpower automation solution that could help with indirect labor and lend a hand in production. We wanted to automate indirect labor functions over time, with the goal of maturing into a 50/50 machine-to-human task force ratio. This would allow us to maintain a “mentor” role over the systems, while having an unlimited workforce on call. Today, we are in the early stages of bringing online portions of the intelligence and weaving them into the daily routines of current team members. Using Neural’s proprietary methodologies, we targeted chunks of these identified networks, and follow system deployment processes to maintain quality adherence. To help with transformation, we utilize an advanced onboarding concept where we operate as a startup within our own company, consuming the processes internally via Smith (SM) (the Artificial Intelligence), to maintain control during the Neural Corps’ Apprentice to Mentor model. We set out to increase our workforce, save time on human processes, and decrease human-to-human networks, which would allow us endless capacity and increased communication speed, which were previously staffed by human-based roles. Smith can provide value in directly realized time equivalent of hundreds of man hours. As it is trained, it evolves, and in time will take on additional duties and solve more problems.

Who should attend: PCB Designer, System Designer, Hardware Engineer, Assembly Engineer/Operator
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
11:00 a.m. - 12:00 p.m.
KEYNOTE: Is Past Prologue? The Future of the PCB Design Industry
Speaker: WALLY RHINES, Mentor

From Racal-Redac’s initial release of a PCB and schematic software nearly 50 years, much has changed in the electronics hardware design space. Routing has become shape-based and automated. Features like component libraries, panelization, design for manufacturing and design rule checks are now the norm. Simulation and analysis tools have been developed and bolted on. And bare boards are no longer conceptualized independently, but rather considered as part of the full system.

As much as the tools have changed, so has the industry itself. Starting as offshoots of larger OEMs, then evolving to a broad mix of independent software developers – some large publicly traded entities, some tiny firms – the tool industry has of late been see consolidation. As mega-mergers such as Siemens’ acquisition of Mentor Graphics take place, will the companies that make tomorrow’s tools once again be parts of large, multinational conglomerates?

Perhaps no one is better positioned to chart the course of these industry changes than Wally Rhines. Rhines led Mentor for more than 24 years, making him easily the longest-tenured executive in the PCB industry history. In this one-of-a-kind keynote address, Rhines will recap the PCB design industry timeline, from its unheralded early days to its current prominence. And he will lay out Siemens’ strategy for Mentor, and how it will shape the industry at large. 

 
F4: Designing in the Age of Prototypes
Speaker: Milan Shah, Royal Circuits

We live in an increasingly connected world with new electronics products introduced every day. From coast to coast, engineers are designing everything from life-changing medical devices to new military technology to one-of-a-kind experiments for launch into space. To stay ahead of competitors, companies must be innovative and quick to market. And once a product is launched, designers must immediately start working on the next revision. PCB prototypes play a critical role in this design-revise-design product lifecycle. Prototypes are the first step in bringing new ideas. Yet, getting PCB prototypes fabricated and assembled correctly on-time and on-budget is a challenge. In this panel presentation, three CEOs from some of the industry’s most respected PCB prototype manufacturing companies will discuss the challenges of PCB prototypes. Executive speakers will be Milan Shan, president of Royal Circuit Solutions; Lawrence Davis, president of Advanced Assembly, and Scott Kohno, president of Royal Flex Circuits. Drawing on nearly 45 combined years in the industry, these executives will also share practical tips, advice and resources on how to get PCB prototypes manufactured on-time and on-budget. Topics to be covered include the latest trends in PCB prototyping; growing usage of flex prototype circuit boards; common PCB fabrication and assembly mistakes; cost-saving design tips; review of different types of PCB prototyping services.

Who should attend: PCB Designer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
1:00 p.m. - 2:00 p.m.
F5: Industry 4.0 and IPC-2581
Speaker: Hemant Shah, IPC-2581 Consortium

Listen to experts from the IPC-2581 Consortium and from IPC-Connected Factory Exchange (CFX) group about Industry 4.0 and what role IPC-2581 plays in it.

Who should attend: PCB designers
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
1:00 p.m. – 3:00 p.m.
F6: The 10+ 21 Most Common Design Errors Caught by Fabrication (and How to Prevent Them)
Speaker: David Hoover, TTM Technologies

In preparation for this presentation, we talked to many of the largest PCB manufacturers in the US and abroad. We then developed a list of the most common errors found on incoming designs. We started with 10 and now, based on popular demand, we've expanded and keep updating that list! We look at each of the errors and discuss ways to find them before the designs are sent out for manufacturing. Methods we will look at include netlist comparison, design for manufacturing, and design rule analysis. We encourage attendee participation and ask folks to bring their challenges for discussion. After this seminar, the PCB designer will take back some knowledge to better assist them in using their existing tools in the market to produce better and more accurate designs.

Who should attend: PCB Designer, Fabricator Engineer/Operator
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
2:00 p.m. - 3:00 p.m.
F7: Efficient PCB Interposer Design Using a Novel Smart Router Based on Neural Networks and Genetic Algorithms
Speakers: Xiao Ming Gao, Intel

As the complexity and variety of system-on-chip (SOC) and IPs development increase, the platforms used to validate silicon electrical and functional performances are becoming increasingly difficult, due to time-to-market and cost constraints. To completely validate these SOC IPs, different platforms have to be designed to target different market segment requirements. Often the time to launch is critical to make sure it will not miss market opportunities. To meet these challenges, the interposers can provide flexible and low-cost solutions. It can be used to adapt silicon to a variety of platforms without changing exiting designs and therefore maximize the return on investments. For example, the N-1 interposer is a special kind of PCB adapter that allows prior generation chip, the N-1 silicon to be installed on a current generation system, the N platform for validations. This facilitates platform checkout and deployment before new silicon arrival, enabling early shift left platform strategy, such as Firmware development, BIOS, and test and validation collateral developments. The design of N-1 interposer involves a few steps. First is to collect requirements and define the pin mapping between N and N-1 generation silicon. Next is to use scripts to generate netlist using this mapping file. Finally, define the board stackup and create constraints to route these connections. The last step is always labor-intensive and time-consuming because interposer board size is usually very small, and the package has more than a thousand pins, so the High Density Interconnect (HDI) design has to be used. A combination of irregular routing patterns and constraints on critical signals is beyond the capacity of the most modern automatic routing systems, and the routings have to reply on manual interactive layout. To improve the efficiency, we propose a new machine-learning-based routing algorithm. Multiple routing strategies can be run in parallel to help search the solution space of its domain. Each phase is essentially an optimization problem, and we use a Genetic Optimization engine that concurrently searches through multiple design options looking for the global best. We propose using a deep neural net as the fitness function. This neural net is trained by analyzing the features of previous successful design patterns, using hard-coded heuristics, such as crossovers, length, and congestion. Leveraging this process parallel mechanism, multi-core CPU and clusters-based computing resources can be used to evaluate multiple routing strategies at the same time. We have used the new autorouter to test both CPU and PCH N-1 interposers’ layouts. The routing time is reduced from a week of manual routing to only a couple hours using the new router. The course will provide a complete interposer design flow from pin mapping, netlist generation, to final PCB component placement and routing. Focus especially on how to effectively use the proposed smart router to drastically reduce layout time and improve design quality.

Who should attend: PCB Designer, System Designer, Hardware Engineer, SI Engineer, Test Engineer

Course rating: Beginner, Intermediate, Advanced

3:00 p.m. - 4:00 p.m.
F8: Optimizing Hardware for Your IoT Solution
Speaker: Sean Priddy, Creation Technologies

Most of the IoT hype is about how billions of devices will generate huge data streams that must be communicated, stored, and analyzed to provide operational visibility and insights using machine learning and AI over time and large data sets. However, often neglected is the actual hardware required to acquire sensor data, process the data, react to the data, and communicate the data over a network to other devices or the cloud. Frequently, emerging IoT solutions require the development of specialized hardware to accommodate various environmental, processing, localized storage, power, and networking requirements. Learn how to make the appropriate technical choices so your hardware is optimized for your IoT solution.

Who should attend: PCB Designer, System Designer, Hardware Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner
 
F9: PANEL: The Future of PCB Engineers
Speaker: Phil Marcoux, PPM, Moderator

A common comment from everyone involved in electronics supply chain today is the chronic "graying" of the industry, meaning a lack of younger engineers and professionals. Is this a truism? And what recruiting and management techniques are needed to attract – and keep – the millennials? Panelists include Joel Camarda, Amonix.

4:00 p.m. - 5:00 p.m.
F10: 3D Printed Electronics: A New Dimension in Prototyping & Manufacturing
Speaker: Simon Fried, Nano Dimension

3D printed electronics technologies are enabling developers to go from idea to working prototype in just days to enable agile electronics development and innovation. By iterating electronic circuits rapidly in-house, 3D printing will transform electronics development and manufacturing processes. During this session, delegates will learn about the disruptive and transformative effect of 3D printing on electronics design and manufacturing, specifically for the aerospace and defense sector. Understand the challenges and technological advancements needed to achieve next-gen 3D printed electronics that ensure high performance and reliability to meet aerospace and defense industry specifications and standards. Determine the scope of 3D printed electronics for a competitive business strategy, and understand how this technology is creating enhanced workflows, improved time to market and agile hardware development processes. Determine how to introduce agile electronics development processes at every prototyping stage to reduce time-to-market, increase innovation and keep proprietary design information in-house.

Who should attend: PCB Designer, Hardware Engineer, Test Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
 
F11: PANEL: Understanding the AS9100C Standard
Speaker: Peter Bigelow, IMI, Moderator

Confusion appears to be growing throughout the supply chain, as it attempts to sort out just how often first article inspection needs to be performed. Manufacturers and their customers face both additional evaluations and a data avalanche, the result of the surge in acceptable quality limit (AQL) samples of FAI measurements as supplied to the customer, which then must enter, sort and distribute (as needed) all that data. It is one thing to impose requirements on suppliers, but in the case of AS9100D, those requirements might be back-flowing. Is FAI the QA engineer’s revenge? How much inspection is too much? How do you make it work for your supply chain? And does the standard need to change? Panelists: XXX, Raytheon; XXX, TTM Technologies

Wednesday, September 13th - CAD TOOL CORNER – FREE SESSIONS!
1:00 p.m. – 2:00 p.m.
C1: Ensure Your Electronic Design is Reliable and Robust by Simulation – During Schematic, Before Manufacturing and Testing
Speaker: Yizhak Bot, BQR

To verify that electronic boards are free of hidden design errors, manufacturers perform qualification and integration tests before manufacturing. If failures are detected, the manufacturer implements a root cause analysis to detect the design fault, and then turns to redesign, remanufacturing and retesting. These time-consuming efforts delay the product launch and cause the project’s budget to overflow, possibly even leading to project cancellation. In this talk we will describe a new method that will detect hidden design errors by simulation in the schematic phase just before layout, manufacturing, qualification or integration tests. Using the simulator, it is possible to locate hidden design errors that may be discovered as late as during customer use. It also enables tracking of faults in existing products that already operate in the field and are used by customers. An example is a product comprising dozens of PCBs that has been operating in the field for several years, which failed suddenly. During the simulation, the cause of the failure was discovered, and the client verified it in the laboratory. Ostensibly, if the simulation had been performed on time, the problem would be entirely avoided.

Who should attend: PCB Designer, Hardware Engineer, Test Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
2:00 p.m. – 3:00 p.m.
C2: Retargeting Your Libraries for Newer, Better Processes without Breaking Your Bank
Speaker: Vince Di Lello, Cadence Design Systems

Libraries hold a company’s IP, most companies will say. Libraries are built for a process that gets outdated. Manufacturing advances and newer fabrication techniques (HDI, embedded) require footprints to be built differently. This talk will show a new methodology and tools to retarget libraries for newer processes in days instead of months/years.

Who should attend: PCB Designer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
3:00 p.m. – 4:00 p.m.
C3: Designing PCBs in the Context of a System
Speaker: Gary Hinde, Cadence Design Systems

System design with multiple boards is a team activity for most companies. Traditional design methodologies force PCB Designers to work in silos that result in identifying system level integration issues late in the cycle or through mid-stream design reviews. There is a better way. This presentation will show a methodology that allows for managing critical high-speed system-level signals, as well as dealing with collision issues between multiple boards in an enclosure.

Who should attend: PCB Designer, System Designer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
4:00 p.m. – 5:00 p.m.
C4: Multi-Domain Collaboration for Electronics Systems Design
Speaker: David Wiens, Mentor

System-level product optimization requires teams across all disciplines of product development efficiently collaborate; this includes mechanical, electronics and electrical domains. This approach runs counter to the conventional “black box” design process, where teams operate largely autonomous from each other, coming together only at the end to validate the total system. Even when teams have tried to collaborate during the design process, they have been faced with tool incompatibility barriers, lack of a common review platform, and inconsistent system constraints. This session will discuss efficient methods of multi-domain collaboration, with a focus on how it enables ECAD, MCAD and cabling design teams to optimize electronics systems.

Who should attend: PCB Designer(Beginner, Intermediate, Advanced): Intermediate

 

Thursday Sept 13th

Thursday, September 13th
8:00 a.m.
Conference Coffee Break, Sponsored by Sierra Circuits
8:30 a.m. – 12:00 p.m.
34: Design of Power Distribution and Decoupling
Speaker: Rick Hartley, RHartley Enterprises

The power distribution section of a PCB is the foundation around which all things work in the circuit. If not designed correctly, the entire circuit is at risk from noise, to say nothing of the severely increased possibilities for EMI. Low impedance in the power bus of a digital circuit across the range of harmonic frequencies is critical. To further complicate matters, analog and digital circuits often need a much different approach for power delivery to ICs.

This course will cover the role of the major components in the power distribution network (PDN), the impact of inductance on the network, the inductance of vias, capacitors and planes, optimum location and mounting configuration for capacitors, energy delivery to IC cores and to I/O drivers, decoupling PCBs with routed power rails / PCBs with widely spaced planes / PCBs with closely spaced planes, impact of IC design on power delivery, ferrites in the PDN, analog power delivery, the real impact of ultra closely spaced planes and the huge impact of board stack-up.

Who should attend: PCB Designer, Circuit/Hardware Engineer, Signal Intgrity Engineer, System Engineer
Course rating (Beginner, Intermediate, Advanced): Intermediate, Advanced
 
35: Part Placement Choices and Consequences
Speaker: Susy Webb, Fairfield Industries

There are many ways to place parts on any board, but clearly some ways work better for physics, electrical, and mechanical purposes. If a new board works electrically but won’t interface properly with the rest of its system, it may require costly and time-consuming re-design and re-testing. Designers must understand the board, electrical and system needs, as well as typical placement and routing guidelines, and the consequences of not adhering to them. When they understand the reasoning behind these things, and the effects they have on one another, designers will intuitively know how to make good decisions for their own board designs, and so avoid problems. In this presentation, we will discuss choosing effective parts, approximate order of overall placement, placement to set up routing, board and system consequences, manufacturability, and more. 

Who should attend: PCB Designer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
9:00 a.m. – 10:00 a.m.
36: Intelligent DfM for Assembly
Speaker: Kevin Webb, Mentor

Design for manufacturing (DfM) applications have been around for many years and have helped companies reduce product costs, improve quality and get products to market faster. However, PCB assembly analysis has always been difficult to align internal rules to manufacturing supplier’s rules. This session discusses a new approach for implementing Assembly DfM analysis. Assembly DfM applications today must be able to intelligently evaluate the component based on many characteristics, such as JEDEC type, body and pin size, pin counts, pin types, etc., to automatically categorize itself for better and consistent DfM rule assignments. Only through an automatic assignment approach can the repeatability of analysis be achieved throughout a design process. This automatic classification approach will permit a consistent set of analyses to be performed in-house, as well as at the manufacturing facility, while considering the manufacturing processes relevant for your PCB assembly. Applications achieving this objective will serve their users better and make the benefits of assembly DfM attainable by a larger audience.

Who should attend: PCB Designer, Other
Course rating (Beginner, Intermediate, Advanced): Beginner
 
37: Providing Solutions for Thermal Management within RF Designs
Speaker: James Barry, PCB Technologies

The presentation will focus on various buildup methodologies to mitigate thermal hot spots. The basics of thermal mitigation will be presented, including heavy copper, internal and external heat sinks, material, and thermal vias. “Coin Technology” and “Air Cavity” will be discussed in depth, including how these buildups can be combined within a structure. Examples of radar boards using Air Cavity will be shown, as well as more complex buildups using a combination of coin, cavity and mixed materials. This presentation will focus on the buildup of products from a cross-sectional point of view.

Who should attend: PCB Designer, SI Engineer
Course rating (Beginner, Intermediate, Advanced): Intermediate
9:00 a.m. – 11:00 a.m.
38: The Mystery of Bypass Capacitors
Speaker: Keven Coates, Geospace

How do you design a high-speed digital circuit with enough bypass caps in the right area to supply all the peak power demands? You can’t listen to all the expert advice because it seems they can’t even agree! This presentation covers power distribution network basics and shows three approaches with simulation results for each, and some real-world experience and advice on bypassing for high-speed circuits.

Who should attend: PCB Designer, System Designer, Hardware Engineer, SI Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
 
39: Ask the Flexperts – Flexible Circuit Design through Test with Lessons Learned
Speaker: Mark Finstad, Flex Circuit Technologies, and Nick Koop, TTM Technologies

This course will cover the gamut of flexible and rigid flex circuits from two of the most recognized names in the industry; Mark Finstad (co-chair of IPC-2223) and Nick Koop (co-chair of IPC-6013). Topics covered will include mechanical design/material selection, cost drivers, bending and forming concerns, testing, and issues unique to rigid flex. Throughout the presentation, the instructors will share many real life stories of flexible circuit applications gained over 30+ years in the industry. Some of these are success stories and others not so much, but all provide excellent lessons learned. The instructors also welcome and encourage questions, and enjoy “wandering off course” with lively interactive discussions on specific topics from the class.

Who should attend: PCB Designer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Course rating (Beginner, Intermediate, Advanced): Intermediate
9:00 a.m. – 12:00 p.m.
40: Designing Embedded Passives and Related Technologies
Speaker: Gary Ferrari, FTG Circuits

We are faced with greater design challenges than yesteryear. Circuit densities and component counts have climbed at an alarming rate. Unfortunately, board area has not increased proportionally. Circuit speeds are increasing, requiring shorter connections and more decoupling capacitors. As a result, embedded passives – those within the printed board structure – have become more attractive. They enable reduced component count, and shorter connections. This session will provide an overview of the various embedded passives technologies.

Attendees will learn how individual embedded discrete components are manufactured, basic design principles for embedded passive devices, and concepts for planar capacitance and resistance layers.

Who should attend: PCB Designer, Electrical Engineer
Course rating (Beginner, Intermediate, Advanced): Intermediate
10:00 a.m. – 11:00 a.m.
Polar Instruments Lunch-n-Learn
(Thursday conference attendees and speakers only)
1:00 p.m. – 4:00 p.m.
41: DfM: Getting it Right from the Start
Speaker: Chris Nuttall, NCAB Group

This seminar describes how to avoid costly production problems with Gerber packages.

Who should attend: PCB Designer, System Designer, Hardware Engineer, Test Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
 
42: Arriving at an Optimal Stackup for Printed Circuit Boards Used in Silicon Validation
Speaker: Vijay Nanjai Anandan, Tessolve Semiconductor

Silicon validation of integrated circuits happens at various levels, such as the wafer, package and system levels. The PCB used for the validation at these levels has different mechanical and electrical requirements. For example, the PCB designed for volume test of ICs needs to be thick enough to remain planar when exposed to high mechanical and temperature stress, whereas PCBs designed for system level or a characterization test, apart from the above, should have better signal and power integrity. Furthermore, PCB fabrication yield has to be high, which has an impact on test hardware cost and cycle time. Arriving at an optimal stackup to meet all these requirements is a crucial part in designing the PCB required for silicon validation. Various stackup technologies used to design these PCBs include plated through-hole with backdrilling; plated through-hole with flip drilling; multi-laminate stackup with blind and buried vias; and high-density interconnect (HDI) stackup with microvias and buried vias. This presentation talks about each of these stackup technologies, their advantages and limitations when it comes to fine-pitch BGA such as 0.35mm, how it suits for a particular device type, be it digital, analog, mixed, PMIC or RF, and their fabrication processes. It aims to expose ATE/system-level test engineers and PCB designers to these stackup technologies, and show how to choose one that best suits for the application and requirements.

Who should attend: PCB Designer, Hardware Engineer, Test Engineer
Course rating: Beginner, Intermediate, Advanced
11:00 a.m. – 12:00 p.m.
43: Leveraging 3-D Layout to Optimize Rigid-flex Designs
Speaker: Craig Armenti, Mentor

2-D design is no longer sufficient for today’s complicated rigid-flex designs. ECAD designers need the ability to leverage 3-D layout in order to properly optimize all elements of a rigid-flex design at the product-level, with the design in its bent state within the enclosure. 3-D layout allows designers to place, route and perform design rule checks with immediate feedback regarding any potential clearance or collision issues. To truly optimize a rigid-flex design, the 3-D environment must be more than just an interpretation of 2-D information; it must provide a realistic view of how the design will be fabricated, no matter how complicated the structure. Properly leveraging 3-D layout functionality also allows the design team to left-shift mechanical validation into the PCB layout stage, making it possible to find and fix electro-mechanical design problems early to eliminate costly, late-cycle redesigns. By considering mechanical requirements during layout and ensuring efficient communication between the electrical and mechanical flows, the rigid-flex design is correctly aligned for manufacturing, avoiding last-minute changes that cost time and money.

Who should attend: PCB Designer, Other
Course rating (Beginner, Intermediate, Advanced): Beginner
 
44: Overview of Several RF Structures and How They Work
Speaker: John Coonrod, Rogers

This presentation will give an overview, in relatively simple terms, of several PCB-based RF structures and will describe the basic operations. Initially transmission line circuits will be discussed, and these types of circuits are often used to connect different RF modules together on a PCB. Expanding on transmission line circuit concepts will be discussions for couplers and filters. Finally, PCB-based antenna designs will be discussed. Basic concepts for each structure will be given, models shown, and measured results compared to model outputs. Most structures will be limited to lower microwave frequencies, but some discussion will be given for millimeter-wave frequencies.

Who should attend: PCB Designer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner
12:00 p.m. - 1:00 p.m.
LUNCH-N- LEARN, Sponsored by Polar Instruments
1:00 p.m. – 3:00 p.m.
45: Electromagnetic Fields for Normal Folks: Show Me the Pictures and Hold the Equations, Please!
Speaker: Daniel Beeker, NXP Semiconductor

The material presented will be focused on the physics of electromagnetic energy basic principles, presented in easy to understand language with plenty of diagrams. Attendees will discover how understanding the behavior of EM fields can help to design PCBs that will be more robust and have better EMC performance. This is not rocket science, but an easy-to-understand application of PCB geometry.

Who should attend: PCB Designer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
1:00 p.m. – 4:30 p.m.
46: Flexible and Rigid-Flex Circuit Design and Assembly Process Principles
Speaker: Vern Solberg, Solberg Technical Consulting

The design guidelines for flexible circuits, although similar to rigid circuits, are somewhat unique. In essence, flex circuits furnish unlimited freedom of packaging geometry, while retaining the precision density, and repeatability of printed circuits. Flex circuits typically replace the common hard-wire interface between electronic assemblies. Flexible circuits, however, have significant advantages over the hard-wired alternative because they fit only one way, eliminate wire routing errors, and save up to 75% on space and weight. Because the flex circuit conductor patterns can maintain uniform electrical characteristics, they contribute to controlling noise, crosstalk, and impedance. The flex circuits will often be designed to replace complex wire harness assemblies and connectors to further improve product reliability. During the half-day tutorial program, participants will have an opportunity to review and discuss the latest revision of IPC-2223, “Sectional Design Standard for Flexible Printed Boards,” which includes base material sets, alternative fabrication methodologies and SMT-on-flex assembly processes. The workshop will also furnish practical flex circuit supplier DfM recommendations for ensuring quality, reliability and manufacturing efficiency. Discussion topics: 1. Applications and use environment • Commercial/Consumer • Industrial/Automotive • Medical/Aerospace • Establishing end-use criteria. 2. Designing flexible and rigid-flex circuits • Flex circuit outline planning • Circuit routing and interconnect methodologies • Fold and bend requirements • SMT land pattern reinforcement criteria. 3. Material and SMT components • IPC standards for flex and rigid-flex dielectrics • Base material and metallization technologies • Selection criteria for SMT components • SMT land pattern development. 4. Assembly processing of flex and rigid-flex circuits • Dimensioning and tolerance criteria • Palletized layout for inline assembly processing • SMT assembly process variations and methodologies • Alternative joining methods for flexible circuits.

Who should attend:PCB Designer, System Designer, Hardware Engineer, Assembly Engineer/Operator
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
1:00 p.m. – 4:30 p.m.
47: Best DfM Practices for Board Engineers
Speaker: Susy Webb, Fairfield Industries

There is so much more to board design than placing parts and connecting the signals electrically. Those who design the board can make a huge impact on the ease of fabrication and assembly just by the practices they put into place as they work. Knowledge and use of standard (best) practices, whether IPC or company standards, ensures that what is sent to the manufacturer will be understood and incorporated with minimal questions, and that can be a real time and cost savings. In this class, we will talk about good practices for building footprints, how parts might be placed for manufacturability, routing practices that are helpful, trace widths and spacings that are producible, a stackup structure that can realistically get the impedance and return needed, and documentation for the manufacturer that is complete and understandable. This presentation is not about how to build a board, but rather about the practical things the board engineer can do to help make fabrication and assembly easier and therefore increase yields and lower the cost for all.

Who should attend:PCB Designer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate, Advanced
 
48: RF and Mixed Signal Board Design
Speaker: Rick Hartley, RHartley Enterprises

This session is intended to give PCB designers an understanding of the “things” RF engineers request during PCB layout. Due to sensitivity in analog circuits, the keys to full functionality (whether designing very high-frequency analog PCBs, mixing RF with digital or mixing low-frequency analog with digital) are signal integrity and noise control in the design of the PCB.

This course will cover impedance matching and balance, signal wavelength, propagation delay, critical trace length, noise, reflections, waveguides and other RF transmission lines, ¼ wavelength couplers and filters designed into board copper, RF/Analog layout techniques and strategies, plane structures, component placement, critical routing and circuit isolation, ground plane splitting (when to and when not to), mismatched loads and other discontinuities, signal splitters, tuning transmission lines, power bus decoupling for RF vs. digital circuits and PCB stackups for mixed RF and digital circuits. (Experienced RF engineers will likely not learn anything new from this course, as the material is mainly geared for PC board designers.)

Who should attend:PCB Designer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate
3:00 p.m. – 5:00 p.m.
49: PCB Design Techniques to Improve ESD Robustness
Speaker: Daniel Beeker, NXP Semiconductor

This presentation will give some simple definitions for ESD/EOS, and describe the important differences in the energy involved and the type of damage that can result. PCB design techniques for improving system robustness will be presented. Some new research to present and some incredible design results to share using these techniques.

PCB Designer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Course rating (Beginner, Intermediate, Advanced): Beginner, Intermediate

 

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