9:00 a.m. – 10:00 a.m.
1: PANEL: Where is the Design Profession Going?
Moderator: Mike Buetow, PCEA

Traditionally printed circuit board designers came from a wide variety of backgrounds. Today, the trend is toward assigning degreed engineers the responsibilities of place and route. How will they balance layout tasks with their other responsibilities? And can training programs keep up? Join an esteemed group of experienced training professionals who will look at trends and offer their thoughts on how today’s design engineers can prepare for tomorrow.

Panelists:

Stephen Chavez, PCEA chairman / Master Instructor

Michael Creeden, PCE-EDU / Master Instructor

Gary Ferrari, Ferrari Technical Services / Master Instructor

Jonah Stephenson, Google (invited)

Jennifer Waskow, Collins Aerospace

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. – 12:00 p.m.
2: Making Intelligent Material Decisions
Speaker: Michael Creeden, CID+, CPCD, Insulectro

The complexity of needs in today’s hybrid circuitry such as RF, HSD and antenna is becoming common to find all types on one board. Learn how innovations with hybrid materials help solve most hybrid circuit challenges. Hybrid boards are not new to the industry, but many of the solutions are based on outdated constructs, and it’s time for innovation. With this presentation, attendees will receive many examples of how to construct and solve a board with most of the concerns of today’s 5G performance challenges: dense high-speed digital, RF and antennas, and many more, addressing HDI solvability, signal integrity/EMI, PDN and improved manufacturability.

Attendees will receive an understanding of basic EM theory with a strong emphasis on material and process solutions that help routing application. This starts with data capture, rules definition, and tool automation, and covers routing perspectives from the start of the layout cycle, all the way to the review and verification stages, into a generation of deliverables for manufacturing. Emphasis is on the role EM fields play to manage your circuit to be cost-effective, perform well electrically and be a reliable high-yield product. We will touch on all types of circuit technologies in many market segments. Focus is on integration between design and manufacturing early in the development cycle, to build a product that is correct-by-construction and performs on Revision-1.

We will cover a wide range of topics, including:

  • Hybrid material selection for rigid, rigid-flex and flex
  • Rationale for considering HDI
  • Placement, routing techniques, power delivery, EMI shielding
  • Technological challenges from design through manufacturing process.

Students will learn what it takes to successfully implement these concerns:

  • Complex solvability
  • High-speed, RF and thermal performance
  • High yield and reliable manufacturability.
Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. – 12:00 p.m.
3: How to Fight Magnetic Noise Gremlins
Speaker: Keven Coates, Fluidity Technologies

Have you ever had a noise-sensitive circuit and tried to find the noise source? Even after you completely encased sensitive portions in all sorts of shielding, you still had noise? It’s very possible this is magnetic noise. Lower frequency magnetic fields can’t be contained and shielded against in the same way electric fields can. In this presentation, hear about the author’s nine-months-long battle with a specific magnetic noise issue, the best tools to fight it, twisted pair, current loops, and the best ways to test for and defeat magnetic noise in your designs. New this year is more on how electric fields compare and some general shielding examples.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. – 12:00 p.m.
4: Best-in-Class for PCB Design
Speaker: Stephen Chavez, Siemens

PCB designers today must take advantage of the automation and horsepower in our respective EDA tools. We just don’t simply “connect the dots” or “push the magic button,” as some may suggest. We design complex PCBs that contain physical packages smaller than ever before, but we are also addressing electrical, mechanical, and thermal variables in a much higher level of complexity due to today’s industry evolution, not to mention the need to design it faster while cutting cost and resources. We are designing PCBs that contain signal speeds and edge rates faster than ever. As if the electrical and mechanical design complexity of a PCB weren’t enough of a challenge, add in manufacturing and producibility complexities on top of that.

All this makes designing entire “complex systems” a true challenge indeed. Simply put, success in PCB design means knowing and understanding what you are doing and how the decisions you make and implement upstream impact downstream ramifications. With today’s EDA tools, harnessing the horsepower and capitalizing on their full capability, when possible, can be a huge difference in getting it right the first time, reducing re-spins (cost), increasing yields, and ultimately getting to market faster.

This session focuses on how to harness the horsepower of your respective EDA tool, and shares a recent success story regarding hardware IP design reuse. We’ll discuss industry best practices within the design process, along with the pros and cons that affect ROI when best practice recipes are implemented and when they are not implemented (the cost of doing nothing).

What You Will Learn:

  • Increase productivity and proficiency with current/future EDA software (automation)
  • Capitalize on existing known good hardware by taking advantage of hardware IP design reuse
  • A success story regarding automation and hardware IP design reuse
Who should attend: PCB Designer/Design Engineer, System Designer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. – 12:00 p.m.
5: From DC to AC – Power Integrity and Decoupling Primer for PCB Designers, Situation Today and Outlook for the Future
Speaker: Ralf Bruening, Zuken

Today, supply voltages decrease with every new silicon generation, contributing as well to the goal of reducing power consumption of electronics. This and the resulting shrinking noise margins for these ICs define increasing demands for the quality and stability of power distribution systems of the PCBs. Shrinking form factors with decreasing board real estate (e.g., IoT devices) and emerging technologies (e.g., autonomous driving, advanced communication units) add fuel to the fire. Hence tighter requirements and constraints from silicon vendors are defined for the power distribution networks (PDN) PCB designers have to follow and implement in conjunction with tighter decoupling schemes. Application-dependent restrictions (e.g., discrete package allowance in automotive) and stringent cost and quality demands further complicate the game.

In this two-hour workshop, the requirements and the basics of PCB power distribution systems are explained in detail. Plate capacitance, loop inductances and cavity resonance are explained without deep math. Side effects to the signal integrity (SI) and EMC behavior of board structures are discussed using illustrated practical examples.

The role of decoupling capacitors and their evolution in recent years are a major part of the workshop. Guidelines for a first order covering and resolving power integrity issues are given regardless of the used PCB design and ECAD process. Simulation capabilities addressing power integrity (PI) during PCB design will be explained and demonstrated by animated slides in a generic, vendor-neutral manner as one powerful problem-solving approach for PI issues. Silicon vendor support documents (e.g., design guidelines, constraint documents, reference designs or spreadsheet tools) to address power integrity are introduced and discussed. Examples from various industries (e.g., automotive) will complement the session with practical application experience.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. – 12:00 p.m.
6: Back-to-Basics: Understand PCB Fabrication Processes for Traditional, HDI, and Ultra HDI
Speaker: Chris Hunrath, Insulectro, and Michael Trammel, Summit Interconnect

Good designers know how their PCBs are fabricated and assembled, and the processes are changing. It is not possible to order a PCB that uses different technologies on different layers, and therefore has different design requirements.

This seminar covers:

  • The basics of traditional PCB fabrication
  • High-density interconnect fabrication
  • Ultra-high-density interconnect fabrication using subtractive, additive, and semi-additive manufacturing techniques.

We will cover all aspects of the process from drill to silkscreen. Then we’ll pivot to cover all aspects of the assembly processes from solder-paste application to inspection and final delivery.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. – 6:00 p.m.
7: PCB Design for Engineers
Speaker: Susy Webb, Design Science

This class will feature an overview of the processes of board design from an engineering perspective. To begin, we will have a conversation about how the electronics and physics are involved and why controlling rise time, field energy, and transmission lines are extremely important to the signals on the board. Placement will be discussed next, with order, flow, and setting up potential routing to come being some of those topics. The planes and stackup structure will play a major role in the quality of the design and impedance control, especially if the design is high-speed, and plane and capacitor placement are a large part of power distribution as well. The way signals are routed and how their return current is set up is critical for their performance.

We will discuss fanouts, using grids, the signal flow from layer to layer, layer-paired routing and spacing. HDI technology can be a huge benefit to dense boards, fine-pitch parts, and BGAs, so we will go over their setup and routing.

All these topics will include information on signal integrity, EMI and impedance control, to make a board that works well from the first build. Many aspects of making a board manufacturable also help to make it less expensive, so an examination of that will wrap up the technical information, followed by information on pros and cons of hand-routing vs. autorouting and the quality of board possible.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Intermediate, Advanced
1:00 p.m. – 4:30 p.m.
8: PCB Designers Guide for Implementing Advanced Semiconductor Package Technologies- Flip-Chip, WLP, FOWLP, 2D, 2.5D and 3D
Speaker: Vern Solberg, Solberg Technical Consulting

This course addresses the design and assembly challenges for developing and implementing flip-chip and multiple function system-in-package (SiP) technology and the new generations of ultra-high-density semiconductor packaging. Driven by the need to maintain a competitive edge and secure a technical advantage in the industry, manufacturers are relying heavily on more innovative IC package solutions.

Although integrating several semiconductor functions onto a single die element (system-on-chip) appears to provide a viable solution for some applications, development cost and time has often proved to be excessive. On the other hand, integrating several mature die or “chicklet” elements into a 2-D or 3-D configured package, however, is actually proving to be superior to the multiple function die because it minimizes risk and significantly reduces development time and cost.

Topics covered:

1. Array package evolution and standards

  • Single die BGA and FBGA packaging
  • Flip-chip and die size package technologies
  • Wafer-level packaging (WLP) JEDEC package outline standards

2. Semiconductor die and package stacking methodologies

  • 3-D wire-bond memory die stacking
  • Homogenous and heterogeneous package stacking
  • Package-on-package variations and standards
  • Package stacking risk assessment

3. Fan-out wafer and panel level packaging

  • Fan-out wafer level packaging
  • Fan-out panel level packaging
  • Mold first panel level process
  • Package outline planning

4. Innovative solutions for 2-D, 2.5-D and 3-D packaging 2-D BGA package technology

  • 3-D Multiple die and stacked package methodologies
  • Implementing 2.5-D for high-density BGA applications
  • Silicon, glass and organic based interposer design

5. HDI circuit and microvia design implementation

  • HDI circuit fabrication variations
  • Microvia process methodology
  • Design guidelines for HDI and ultra HDI circuits
  • HDI sources and economic issues

6. Preparation for robotic assembly processing

  • Basic features needed for SMT assembly processing
  • Palletizing to maximize assembly process efficiency
  • System requirements for accurate device placement
  • Assembly process implementation

The material presented has been developed to better enable the product designer and manufacturing specialist to evaluate a broad number of semiconductor packaging methodologies. The examples shown will furnish both physical and monetary benefits gained using multiple die packaging, as well as adverse concerns related to supply-chain obstacles and infrastructure limitations.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test Engineer, Assembly Engineer/Operator
Target audience:  Beginner, Intermediate, Advanced
1:00 p.m. – 4:30 p.m.
9: Circuit Grounding to Control Noise and EMI
Speaker: Rick Hartley, RHartley Enterprises

When time-varying (AC) signals travel in the transmission lines of a board, state-changing electric and magnetic fields are present. These fields, when not controlled, are the source of noise and EMI. In recent years, ICs with very fast rise time outputs have made problems common, even in circuits clocked at low frequencies. Knowing all the basics of proper grounding will help contain and control fields, making noise and EMI issues virtually nonexistent.

This 3.5-hour course will focus on the issues PCB designers and engineers need to know to prevent noise, EMI and grounding problems in today’s circuits. We will discuss what is meant by “grounding,” where energy travels in the board, location of high- and low-frequency currents, keys to controlling common mode EMI, cables and other unintended radiators, effects of IC style and packaging on overall grounding, impact of connector pin-out, best locations for IO connectors, divided planes and plane islands in the PCB, routing to control noise, best board stack-ups and filtering of single-ended and differential I/O lines.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
1:00 p.m. – 4:30 p.m.
10: An Intuitive Approach to Understanding Basic High Speed PCB Layout
Speaker: Keven Coates, Fluidity Technologies

What is a wire? At high speeds, it behaves very differently from what we were taught in college. This presentation on high-speed basics makes the subject intuitive in a way that’s easily understood. Learn about how frequency enters the picture, high-speed signal propagation, impedance, noise, and reflections with easy-to-understand animations and analogies to understand this subject on a deeper level.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner, Intermediate, Advanced
1:00 p.m. – 4:30 p.m.
11: Effective PCB Design: Techniques to Improve Performance
Speaker: Daniel Beeker, NXP Semiconductor

As IC geometries continue to shrink and switching speeds increase, designing electromagnetic systems and printed circuit boards to meet the required signal integrity and EMC specifications has become even more challenging. A new design methodology is required. Specifically, the utilization of an electromagnetic physics-based design methodology to control the field energy in your design will be discussed. This training module will walk through the development process and provide guidelines for building successful, cost-effective printed circuit boards.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced
1:00 p.m. – 4:30 p.m.
12: Printed Circuit Fabrication Today: A More Complex Process
Speaker: Gary Ferrari, Ferrari Technical Services

Materials, equipment, line widths, impedance, etc. has had a large effect on printed circuit board fabrication. This presentation is for engineers, designers, and anyone who has never been in a board fabrication facility. To this end, over 130 slides have been assembled, including videos, for a virtual walk through the manufacture of a multilayer printed board. In addition, attendees will have the opportunity to handle boards at each level of its production.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
6:00 p.m. – 7:00 p.m.
13: Printed Circuit Engineers Association Annual Meeting

Come learn about the new Printed Circuit Engineering Association, an international network of engineers, designers, and anyone related to printed circuit development. Its mission is to promote printed circuit engineering as a profession and to encourage, facilitate, and promote the exchange of information and the integration of new design concepts through communications, seminars, workshops, and professional certification through a network of local and regional PCEA-affiliated groups.

10:00 a.m. to 11:00 a.m
13 : Optimizing the Tool Chain from Design Through Manufacturing for Printed Electronics
David Wiens, Siemens, and Jeff Bergman, NextFlex

This presentation from NextFlex will review the current variants of additive manufacturing (e.g., flexible hybrids, molded interconnect, conformal print, “true 3-D” structures) and challenges in design for these processes (planar vs. non-planar), and will explain work being done to optimize the tool chain, including changes to design process; different outputs to manufacturing; and manufacturing process prep with tool pathing.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m
14 : Cables and Connectors: Design for Signal Integrity (Will They Work?) and EMI
Keven Coates, Fluidity Technologies

Everyone talks about signal integrity in PCBs, but few circuit boards operate without external wiring. Whether it’s as simple as power wiring, as complicated as high-speed differential pairs, or even worse, non-differential pairs, there are good and bad ways to use the connectors and cables available to us today. This class will show how connectors and cables relate to basic SI concepts. How does the energy flow in the wiring? What determines impedance? How many grounds do I need in the cable? How do I pick connectors? I will go over practical examples showing the tradeoffs, since nothing is completely ideal. This class will shed new light on how we can apply the same signal integrity rules for other things to wires and cabling.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m
15 : Back-to-Basics: Understand the Surface Charge Model of Electricity
Mark Hughes

There is an excellent chance you don’t understand how charges move in conductors or how energy moves in your circuit. Preconceptions you’ve held since high school and college might affect how you lay out printed circuit boards. Don’t worry. You stand in good company with most electronic engineers regarding the preconceptions that lead to bad layout practices. To understand how the energy flows around conductors, students need a different model of charge behavior in conductors than they often learn. Once students understand the physics that describe a conductor’s field, they can understand the lessons that signal integrity engineers have to teach. This seminar will provide engineers with a physics refresher that builds up the surface charge model from first principles. Elementary topics such as energy, field theory, and Ohms and Joule’s laws will be covered. Participants will receive a whitepaper or book that covers the various topics for further review.

Who should attend: PCB Designer/Design Engineer, SI Engineer
Target audience: Beginner, Intermediate
1:30 p.m. to 3:30 p.m.
16 : The Mystery of Bypass Capacitors
Keven Coates, Fluidity Technologies

How do you design a high-speed digital circuit with enough bypass caps in the right area to supply all the peak power demands? You can’t listen to all the expert advice because it seems they can’t even agree! This presentation covers power distribution network basics and shows three approaches with simulation results for each, and some real-world experience and advice on bypassing for high-speed circuits.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
1:30 p.m. to 5:00 p.m.
17 : PCB Antennas for Everyone
Benjamin Jordan, JordanDSP

This half-day course is for professional PCB designers and engineers who want to know all the key factors and processes to design PCB antennas for RF, microwave and ISM-band applications as needed in most modern electronic devices. In the class we will begin with the fundamental principles of operation in a very approachable, intuitive way. This will include many visualizations and animation of the fields and waves to build intuitive understanding of the modes and operation of propagation. This will be built up to involve design parameters and requirements, and we will examine all the most popular antenna types typically used in today’s wireless connected devices. Various tools will be introduced throughout as free options with which to get started (in a noncommercial way). At the end of this class attendees will have confidence to go forth and design PCB antennas. Attendees will have new tools and processes at their disposal, and be far better at collaborating with microwave engineers. You will be confident in designing layer stacks, configuring design rules, and choosing materials for boards that incorporate antennas. There will be practical demos and exercises in the class.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
1:30 p.m. to 5:00 p.m.
18 : Part Placement Choices and Consequences
Susy Webb, Design Science

There are many ways to place parts on any board, but some work much better for physics, electrical and mechanical purposes. If a new board works electrically but won’t interface properly with the rest of its system, it may require costly and time-consuming redesign and retesting.

Designers must understand the board, electrical and system needs, as well as typical placement and routing guidelines and the consequences of not adhering to them. When the reasoning and effects they have on one another are understood, designers will intuitively make good decisions for their board designs and avoid problems. In this presentation, we will discuss choosing effective parts, approximate order of overall placement, placement to set up routing, board and system consequences, manufacturability, and more.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer
Target audience: Intermediate
3:30 p.m. to 4:30 p.m.
19 : Surface Finish Selection Criteria for Next Generation PCB Technologies (5G-HDI-High Frequency-RFMW)- Focusing on Performance & Reliability
Kunal Shah, PhD., LiloTree

The advent and ongoing evolution of internet-enabled mobile devices has continued to drive innovations in the manufacturing and design of technology capable of high-frequency/high-density electronic signal transfer. Selection of materials used in PCB manufacturing is critical for optimum performance and better reliability of the electronic assembly. Among the primary factors affecting the optimum performance and better reliability is the surface finish applied on PCB copper pads.

The talk will cover how surface finish contributes to signal integrity and reliability of next-generation electronic assemblies. Typically, connections (solder joints) between PCBs and surface mount components are prone to brittle failures. One of the parts of the course will be to evaluate how surface finish can lead to robust solder joints and better reliability of electronic assemblies. Also, the selection criteria of surface finish for next-generation PCB technologies – 5G, high frequency, HDI, RF-microwave applications, etc. – involves minimal insertion loss, long shelf life, and cost-effective and better reliability. There are a few options (EPIG, EPAG, DIG, etc.) available in the market, and their pros and cons will be discussed.

Moreover, an innovative nickel-less approach involving a proprietary nano-engineered barrier designed to coat copper contacts, finished with an outermost gold layer, has shown superior benefits over contemporaries.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Intermediate, Advanced
9:00 a.m. to 10:00 a.m.
F1: PANEL: How Heterogenous Integration Affects the PCB Industry
Moderator: Phil Marcoux
 
Heterogeneous is the latest branding effort to promote the assembly of dissimilar electronic components. In the past these could be called multichip modules, 2.5-D, 3-D and – really going back – “hybrid” assemblies. How the selected components are interconnected drives how they are assembled and what substrate materials will work.

As with any new set of tools, it’s necessary for users, especially designers, to know what they can and can’t use easily, economically or reliably. It’s equally important for anyone wanting a heterogeneous assembly to understand the consequences resulting from the interconnections and materials chosen, and to realize that currently they are available from a limited base of capable assemblers.

Heterogeneous integration makes the design function much more complex than is typical for electronic products, however, because many parameters can impact performance. This panel will address those complexities and how to solve them for printed circuit board designs.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Fabrication Engineer, Assembly Engineer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 11:00 a.m
F2 : Dynamic Guidelines for Design with SAP (Semi-Additive Processes)
Tomas Chester, P.Eng, CPCD, Chester Electronic Design and Tara Dunn, Averatek

This presentation will explore the unique challenges associated with designing for new semi-additive PCB fabrication techniques and offers a framework for maximizing those benefits. These are not hard and fast design rules, but dynamic guidelines for PCB design from a new perspective.

For many of today’s circuit designs, traditional subtractive etch processes for manufacturing printed circuit boards are adequate. Traditional technology has constraints, typically limiting conductor line widths and spaces to 3 mils/3 mils (75 micron/75 micron). New semi-additive process (SAP) technologies can reach much smaller pitches, typically 1 mil/1 mil and below. While SAPs are a great tool for the design toolbox, resetting the technology curve and opening additional freedoms in PCB design, there is a learning curve to navigate.

This presentation will explore the most frequently asked questions and lessons learned. Questions addressed will span from simplistic questions such as how to address plated through-holes and microvias to more involved concepts when using SAP layers and subtractive etch layers in the same stack-up, finishing with much more complex issues related to signal integrity concerns and optimizations.

This presentation will conclude by fielding audience questions related to designing with these ultra-high-density feature sizes.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 11:00 a.m
F3 : Understanding High Frequency Materials Test Methods for Dk and Df
John Coonrod, Rogers Corp.

Many different test methods can be used to determine the dielectric constant (Dk) or dissipation factor (Df) for a high-frequency circuit material. It is possible to test the same circuit material using two different test methods, get two different answers, and both answers are correct. This statement can be very confusing and frustrating for those less familiar with the high-frequency material test methods. However, when the test method is well understood, as well as the basic properties of the material being tested, a clear understanding of the results can be achieved. This understanding is critical for engineers when choosing high-frequency circuit materials, especially when comparing data sheets using different test methods. This presentation will discuss many different test methods used to evaluate high-frequency circuit materials for Dk and Df. The presentation will start with a simple overview of test method concepts and provide examples of different test methods used at microwave frequencies. Some test methods discussed will be for testing raw dielectric material, and other methods will use circuit testing to obtain Dk and Df properties. Following this discussion will be test methods used for millimeter-wave frequencies with examples.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, RF Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced
11:00 a.m. to 12:00 p.m.
F4 : KEYNOTE: Augmented and Virtual Reality, the Next Computer Revolution
Brian Toleno, Ph.D., Meta

The metaverses offer myriad opportunities not just for users but for developers of computing devices. As that market takes off, what novel innovations in materials and production will be needed for printed circuit designs to meet the requirements for weight, size, and functionality?

Those are the questions Dr. Brian Toleno, manager, materials technology at Meta Reality Labs, will tackle when he keynotes this year’s PCB West conference. His talk, Augmented and Virtual Reality, the Next Computer Revolution, will describe the current market, use cases, and the technology all around AR/VR, with a focus on the printed circuit board aspects.

At Meta, Dr. Toleno leads a multi-disciplinary team that works on the material challenges in Meta’s consumer electronics hardware. These devices include VR headsets, smart glasses (Ray-Ban Stories), Portal smart screens and other exciting devices that help bring people together.

 
 
1:30 p.m. to 2:30 p.m.
F5 : Evaluating Emerging PCB Technologies Through Industry Collaboration
Madan Jagernauth, HDP

The rapid evolution of enabling technologies requires the independent evaluations of new PCB fabrication, assembly, and test technologies; such evaluations are time-consuming and require significant resources. A collaborative approach offers opportunities to perform evaluations efficiently, reducing cost and improving time-to-market for the ever-increasing demands for higher performance, higher speed, higher density packaging and improved reliability. High Density Packaging User Group (HDP) provides its members with opportunities for unbiased comparisons not found in the literature through member-driven projects. This presentation provides a view of the opportunities for industry collaboration in several areas: for example, new materials for high-speed packaging, next-generation optical integration, next-generation solder alloys, new package technologies, new methods for reliability assessment and higher copper density technologies.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test Engineer
Target audience: Intermediate, Advanced
1:30 p.m. to 3:30 p.m.
F6 : The 21 Most Common Design Errors Caught by Fabrication (and How to Prevent Them)
Ray Fugitt, DownStream Technologies, and David Hoover, TTM Technologies

In preparation for this presentation, we talked to many of the largest PCB manufacturers in the US and abroad. We then developed a list of the most common errors found on incoming designs. We started with 10, and based on popular demand, we’ve expanded and keep updating that list! We look at each of the errors and discuss ways to find them before the designs are sent out for manufacturing. Methods we will look at include netlist comparison, design for manufacturing, and design rule analysis. We encourage attendee participation and ask folks to bring their challenges for discussion. After this seminar, the PCB designer will have knowledge to assist them in using their existing tools to produce better and more accurate designs.

Who should attend: PCB Designer/Design Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
2:30 p.m. to 3:30 p.m.
F7 : Leveraging CFX-QPL to Integrate Equipment and Create a Smart Factory
Ivan Aduna, Koh Young

Leveraging IPC-CFX, Koh Young can use AI-powered technology to help manufacturers realize a smart factory. These tools collect factory data on defects, optimization, traceability, and more to improve metrics, increase quality, and lower costs. Yet, successful CFX implementation on the shopfloor requires confidence that equipment has been qualified to IPC-CFX using the QPL certification platform. In this paper, we will explore how Koh Young successfully applies real-time data to improve the production process by converting data into process knowledge using CFX and other software tools. Combined with IPC communication standards, the gates to a smart factory are open to anyone.

Who should attend: System Designer, SI Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Intermediate, Advanced
3:30 p.m. to 4:30 p.m.
F8 : The A+ PCB Outline Drawing
Carl Schattke, PCB Product Development

This class will save design teams time and money and prepare them for optimal communication for a fast start to the design process. All the important points of the PCB outline drawing will be reviewed, so attendees will know what to look for and what to ask for when creating or receiving an outline drawing. The details of what should be on the outline drawing will be shown and listed so attendees will gather the proper information.

Emphasis will be placed on design details, including dimensions, tolerancing, hole call-outs, component marking, and critical features for manufacturing and cost control. Keep-out designations, height requirements. Drawing formats and outputs. The author intends to leave attendees a much higher level of understanding the critical aspects of starting a PCB design the right way.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced
3:30 p.m. to 4:30 p.m.
F9 : IPC-2581’s Bi-directional Electronically Executable DFx Exchange Accelerates NPI
Hemant Shah, IPC-2581 Consortium, and Dana Korf, IPC-2581 Consortium

Digital Product Model Exchange (a new name for Generic Requirement for Printed Board Assembly Product Manufacturing Description Data and Transfer Methodology) introduces new features, automation supporting Industry 4.0, and bidirectional DFX intelligence capability that eliminates the back and forth between design house and manufacturers before production begins.

Revision C includes the bidirectional DFX data exchange through which feedback between design and manufacturing is conveyed and tracked before manufacturing begins. IPC-2581C is also a major component of the digital twin architecture and strategy, setting the standard for interoperability between different digital twin solutions, bringing maximum value from data.

IPC-2581 revision C is much more than an incremental update, providing the industry’s only fully digitalized and automated data exchange. It is ready to be a critical part of any PCB fabrication and assembly manufacturing smart factory strategy.

This presentation will educate attendees about the following:

• A brief overview of 2581, particularly about revision C

• What’s new in revision C at a high level

• Why use IPC-258: benefits to design houses and to manufacturing houses

• Who supports IPC-2581?

• The IPC-2581 journey and who can help you along the way

Who should attend: PCB Designer/Design Engineer, Test Engineer, Fabricator
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
20 uHDI Design Process Overview and PCB Fabrication

Ultra-high-density interconnects (UHDI) allow trace and space with below 50 microns and vias with 75-mil pads. In other words, vias the diameter of a human hair. But uHDI semi-additive processes can be combined with traditional HDI semi-additive processes and traditional subtractive PCB fabrication processes. In other words, designers can have different trace/space widths on each layer of their design because they use different processes on each layer of their design. This reduces layer count and overall cost.

This presentation will cover material science and manufacturing processes for HDI and ultra HDI designs. Chris Hunrath will cover the material science and availability of the next-generation materials, and Herb Snogren will discuss the fabrication processes and techniques needed for designs of each individual process.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
21 PCB Layout of Switch Mode Power Supplies
Rick Hartley, RHartley Enterprises

When executing PCB layout, we tend to treat digital circuits differently from analog circuits. Each has its own critical requirements. Switch mode power supplies are another wrinkle altogether, and usually need to be treated differently from either.

All switch mode power supplies have four to five circuit loops, all of which are important, but a couple of these loops are downright critical in terms of PCB layout. An improperly designed switch mode supply will often not function as intended, and in some cases will not function at all. In contrast, understanding what makes up a switcher circuit and knowing how to take care of the loops during board layout will permit these supplies to operate flawlessly with very high efficiency.

This two-hour course will outline the difference between switchers and series-regulated power supplies, the different types of switcher circuits (buck, boost, etc.), basic theory of operation of switcher circuits and the impact of the various components, definition and behavior of the five loops, layout to isolate loops from one another, minimize voltage drop, and control current paths, layout to minimize noise and EMI, effect of paralleling output capacitors and proper grounding technique.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
22 Electromagnetic Fields for Normal Folks: Show Me the Pictures and Hold the Equations, Please!
Daniel Beeker, NXP Semiconductor

We all are involved with developing products that generate, control, and consume electromagnetic field energy. This is not what we are taught.

Circuit theory suggests electrical energy is made up of electrons moving in the conductors. Switches add conductors, and the current instantly starts to move in the loop. The wires carry the energy, and the load instantly responds to the flow of energy.

Wrong!

Switches add new spaces, and the moving field carries the energy. It takes time for the field energy to move into that space. The moving field energy has no idea of what it is at the end of the new space. Field energy moving through a space is the current flow. The magic here is the displacement current flowing through the dielectric at the wavefront, completing the circuit. Fields do all the work. “Current flow” is a measure of moving field energy through a space. “Current flow” occurs in the space between the conductors that bound the dielectric. Some of the fields interact with the molecules in the outer surfaces of the conductors. This interaction consumes some of the field energy, hence a resulting voltage drop caused by this “resistance.”

The consumption of field energy results in increased movement of the molecules, hence converted to heat! The dielectric also consumes energy the same way, unless it is a vacuum. Electromagnetic energy appears to move slower through a physical dielectric than through space. Field energy can only travel in space, not through matter. It takes time for the energy to go around the molecules it encounters. The higher the molecular density, the longer the path. Therefore, it takes the field longer to go from one place to another. Once created, EM field energy can only move from one space into another one as we intend, be converted into kinetic energy, or radiated into the surrounding spaces.

This course will provide an easy-to-understand description of the behavior of electromagnetic field energy. This understanding is critical to the development of properly functioning, compliant products. The material presented will be focused on the physics of electromagnetic energy basic principles, presented in easy-to-understand language with plenty of diagrams.

Attendees will discover how understanding the behavior of EM fields can help design PCBs that will be more robust and have better EMC performance. This is not rocket science but an easy-to-understand application of PCB geometry.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
23 Ask the Flexperts — Design-to-Test with Lessons Learned
Mark Finstad, Flexible Circuit Technologies, and Nick Koop, TTM Technologies

This course will cover the entire gamut of flexible and rigid-flex circuits from two of the most recognized names in the flexible circuit industry: Mark Finstad (co-chair of IPC-2223) and Nick Koop (co-chair of IPC-6013). Topics covered will include mechanical design/material selection, cost drivers, bending and forming concerns, testing, and issues unique to rigid-flex.

This course also includes a complete virtual plant tour of a flexible circuit manufacturing facility to help attendees understand the manufacturing processes. Throughout the presentation, the instructors will share real-life stories of flexible circuit applications gained over 35+ years in the industry. Some are success stories, others not so much, but all provide excellent lessons learned.

The instructors also welcome and encourage questions and enjoy wandering off-course with lively interactive discussions on specific topics from the class.

Who should attend: PCB Designer/Design Engineer, System Designer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
24 Improving Circuit Design and Layout for Accessibility and Success
Tomas Chester, Chester Electronic Design

With this seminar, attendees will be given details and examples of additional information that can be embedded within their existing design process. This content is aimed at improving the successful outcome of their design and reducing the time spent acquiring circuit, component, or layout knowledge. Whether you are a solo designer or an engineer within a large team, these design additions will enable participants to look beyond their own immediate workflow and improve the project design process.

The seminar will focus on:

• Project foresight

• Multi-channel/multi-project design reuse

• Identical characterization during the entire development cycle.

The following topics will be covered:

• Component/library creation for future/multi-project use

• Schematic accessibility and complexity reduction • Printed circuit schematic and layout design strategies for verification and debug

• Procedural interactions of a successful project.

Attendees will gain methods for improving design success:

• Design examples and experience interacting with various project states

• Methods for reducing verification and debug cycles

• Multi-user interactive perspectives.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test Engineer, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 7:00 p.m.
25 A Guide to RF and Microwave PCB Design
Benjamin Jordan, JordanDSP

Attendees of this class will leave with a far better understanding of the intricacies of RF and microwave PCB layout and engineering. This class will help PCB designers, embedded hardware developers, and systems engineers get a fresh and intuitive understanding of RF and microwave signals as they operate in the PCB.

The beginning is a review of fundamental field and wave principles in a visual and intuitive context, with simulations and animation to help bring the topic to life, followed by discourse on all the most necessary and common RF/microwave structures implemented within a PCB, their theory of operation, and design parameters.

Included in the class, we will introduce:

  • Visualization of fields and waves
  • Essential calculators (free!) for design
  • Propagation as related to PCB layout
  • Impedance, RLCG and loss
  • Materials for RF
  • Layer stack design for RF
  • Impedance matching techniques
  • Intro to the Smith chart
  • Intro to S-parameters
  • Essential structures (stubs, dividers, transformers, filters, etc.)
  • Intro to RF/MW PCB simulation using free software (as time permits)
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate
1:00 p.m. to 2:00 p.m.
26 Panel: Emerging Technologies and Their Impact on Manufacturing
Moderator: Tara Dunn, Averatek

While new technology adoption is often slow by design, over time we see ample examples of innovations that have become mainstream. What technologies will influence the way electronics are designed and built in the next five years?

Our panel will look at a combination of material and digital changes ahead, from factory level materials to augmented reality possibilities, with an emphasis on how these technologies might change the way electronics are built.

  • Tomas Chester, Chester Electronic Design
  • Liam Cadigan, Cadence / InspectAR
  • Sheldon Fernandez, DarwinAI
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
 
2:00 p.m. to 3:00 p.m.
27 HDI Via Design: Planning the Energy Pipelines
Daniel Beeker, NXP Semiconductor

This session will focus on the challenges posed by using HDI vias from the perspective of layer transitions and power delivery. The example will use a 12-layer PCB to discuss the requirements for signal layer transitions. Via stackups will be defined to enable good signal integrity. Power delivery and the via structures necessary will also be addressed. A must-see class for anyone planning to use this technology.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
2:00 p.m. to 5:30 p.m.
28 Where Does Today’s Designer/Engineer Start? Has The Industry Really Changed That Much?
Gary Ferrari, Ferrari Technical Services

This presentation will discuss the differences between yesterday’s requirements vs. today’s requirements. Board requirements differ from one design to another. With the introduction of new materials, fabrication processes, testing capabilities, and assembly capabilities, one must completely understand the differences as applied to current technologies. Today’s designer/engineer will need to fully understand working with surface mount and through-hole technology on the same board structure to meet today’s challenges.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
2:00 p.m. to 5:30 p.m.
29 IoT and Low Layer Count PC Board Design
Rick Hartley, RHartley Enterprises

Circuit boards for the IoT (Internet of Things) world are often driven by the need for low power dissipation, low cost (which drives very-low-layer count), moderate- to high-density and mixed-signal applications. This combination of needs can make the board design an extreme challenge.

Creating a 1-, 2- or 4-layer board with excellent signal integrity and low noise/interference and no EMI issues can, by itself, be a serious challenge. This 3.5-hour course will discuss when it is necessary to control impedance of lines, how to do it cost-effectively, proper setup of routed lines to keep circuit energy from spreading (preventing interference), even on a one-layer board, design of antenna into the PCB, circuit grounding in low-layer-count boards, power distribution without the benefit of power planes, ground bounce, and crosstalk with low-layer-count PCBs.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner, Intermediate, Advanced
2:00 p.m. to 5:30 p.m.
30 Heat Management for SMD, LED, and systems 1W to 50W
Keven Coates, Fluidity Technologies

Do you use power MOSFETs, high-power LEDs, power resistors, or hot processors in your design and want to avoid heat-related system failures?

This course covers the best options for you to manage heat cost-effectively and reliably. It provides a good overview of PCB design to maximize SMD/LED heat dissipation. It also covers how to choose the right heat sink interface materials, heat sink designs, natural and forced airflow options, as well as heat dissipation simulations (both mechanical and in software).

We’ll go over some helpful tools, and break down thermal resistance equations to simple terms. Heat management doesn’t have to be scary. Take this class to know your options. Now with LED specifics!

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner, Intermediate, Advanced
2:00 p.m. to 5:30 p.m.
31 Designing Boards with Today’s BGAs
Susy Webb, Design Science

Fanout and routing of today’s BGAs can be quite challenging! It may require a lot of creativity to set up the patterns of signals and vias needed to get all the connections out of the parts. Doing that while trying to maintain a good return path, signal integrity, and EMI and crosstalk control can be even more complicated. Additionally, manufacturing concerns are unique to the newer BGAs because of their small pad sizes, the trace widths needed, and the small capacitors used.

In this presentation, we will discuss all those and more, including choosing effective BGAs, the placement of caps, power and stackup information that might be helpful, and grid systems for through-hole and microvia fanout.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
32 Principles of Building a PCB Stackup
Susy Webb, Design Science

The stackup of a printed circuit board is one of the most important parts of the design layout. It affects the way the signals flow on the board, so it can affect many other aspects of the functioning board, like impedance control, return current, and the amount of crosstalk, common mode currents and displacement currents there are. In today’s higher speed designs, it is critical to do this step well, so we will discuss the things needed for a good stackup, and the routing thereon, both from an electronic and a manufacturing perspective.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
33 Mechanical Design to Control EMI
Rick Hartley, RHartley Enterprises

As most engineers and designers are aware, EMI occurs because some mechanical structure, within or attached to our system, is capable of resonating and radiating electromagnetic field energy. Those mechanical structures can be a cable attached to the enclosure around the circuit, a part of the metal chassis, a slot in the chassis or a portion of one of the circuit boards in the system. Knowing how to control these structures so they are not capable of supporting resonance and radiation is the key to success.

This two-hour course will discuss basic physics of energy movement, metal vs. plastic enclosures, slots and openings in enclosures, shielding enclosures, shielding of components, proper shielding of cables, basic component placement for mechanical engineers (MEs), extreme importance of I/O connector placement, routing of external cables, position of cables inside the system, multiple boards in the system, best arrangement, using chassis as a heatsink, and other items MEs and PCB designers need to know about PCBs and the system.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
34 Fan-Out Wafer/Panel-Level Packaging (FOW/PLP) and System-in-Package (SiP)
John H. Lau, Ph.D., Unimicron

Fan-out wafer/panel-level packaging (FOW/PLP) has been getting a lot of traction since TSMC used their integrated fan-out (InFO) to package the application processor for the iPhone 7. In this lecture, all aspects of fan-out packaging will be presented and discussed. Emphasis is placed on the fundamentals and latest developments of these areas in the past four years. Their future trends will also be explored.

System-in-package (SiP) or heterogeneous integration (HI) uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (side-by-side and/or stack) with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem. For the next few years, we will see more implementations of a higher level of SiP/HI, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the introduction, recent advances, and trends in SiP/HI and HI will be presented.

Who should attend: PCB Designer/Design Engineer, System Designer, Assembly Engineer/Operator
Target audience: Intermediate, Advanced
1:00 p.m. to 3:00 p.m.
36 The Mechanical Side of PCBs
Tomas Chester, Chester Electronic Design

All PCB projects have mechanical and physical parameters, from their size to how they are supported within their utilization, which have downstream impacts within our digital thread. This seminar will take an in-depth look at a variety of existing EDA design tools and new mechanical methods that can be harnessed to yield a successful final product, while also examining the impact of stresses on the layer stackup. Whether you are a solo designer or an engineer within a large team, the material covered will enable participants to identify and solve complex design problems.

This seminar will focus on:

  • Existing implemented mechanical PCB features
  • Advanced PCB fabrication techniques
  • Thermal solutions in the mechanical domain.

The following topics will be covered:

  • PCB mounting holes and backdrilling
  • Cross-sectional strength of stackups
  • Thermal transfer within PCBs and impact of heatsinks
  • Semi-flex and multi-stackup stepped PCB construction.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
1:00 p.m. to 4:30 p.m.
38 Circuit Design Principles for Flexible and Rigid Flex Circuits- Planning, Design, Fabrication and Assembly Processing
Vern Solberg, Solberg Technical Consulting

The design guidelines for flexible circuits, although similar to rigid circuits, are somewhat unique. In essence, flex-circuits furnish unlimited freedom of packaging geometry while retaining the precision density and repeatability of printed circuits. Because the flex-circuit conductor patterns can maintain uniform electrical characteristics, they contribute to controlling noise, crosstalk, and impedance. The flex-circuits will often be designed to replace complex wire harness assemblies and connectors to further improve product reliability and have a significant advantage over the hard-wired alternative because they fit only one way, eliminate wire routing errors, and save up to 75% on space and weight.

During the half-day tutorial program, participants will have an opportunity to review and discuss the latest revision of IPC-2222 and PC-2223, Sectional Design Standard for Flexible Printed Boards that include base material sets, alternative fabrication methodologies and SMT-on-flex assembly processes. The tutorial also furnishes practical flex circuit supplier DfM recommendations for ensuring quality, reliability and manufacturing efficiency.

Topics of discussion:

 
  1. Flexible circuit applications and establishing end-use criteria
    • Commercial/Consumer
    • Industrial/Automotive
    • Medical/Aerospace
    • Establishing end-use criteria
  2. Base material and flexible circuit fabrication processing
    • IPC standards for flex and rigid-flex dielectrics
    • Base material and metallization technologies
    • Preparing for flexible circuit fabrication
    • Addressing fabrication supplier capability
  3. Flexible and rigid-flex circuit planning and DfM design principles
    • Flex circuit outline planning
    • Circuit routing and interconnect methodologies
    • Static fold and bend requirements
    • Dynamic bend prerequisites
  4. SMT component selection and land pattern development
    • SMT component land pattern development
    • Passive components
    • Leaded SMT semiconductors
    • QFNs
    • Array packaged semiconductors
    • SMT component mounting and area reinforcement criteria
  5. Documentation for flexible and rigid-flex circuit fabrication
    • Dimensioning and tolerance criteria
    • Defining primary physical features
    • Developing the fab detail for inspection
    • Preparing detailed requirements for fab
    • One and two copper layer flex
    • Combing flexible and rigid material
  6. Preparing for automated inline SMT assembly processing
    • Conveyor handling of complex flexible circuit shapes
    • Palletized flexible circuit array for robotic assembly
    • Features and documentation required for robotic assembly
    • Surface mount assembly process sequence
    • Alternative SMT solder methodologies

Course objectives:
This tutorial has been developed to furnish the design professionals, systems engineers, and assembly and test engineering specialists with a thorough understanding of the materials, fabrication process variations and preferred design practices for flexible and rigid-flex circuits detailed in IPC-2222 and IPC-2223 standards. In addition, the requirements for automated SMT assembly will be defined and include detailed discussion regarding panel planning and SMT assembly process variations.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test Engineer, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
1:00 p.m. to 4:30 p.m.
39 A Multilayered Crash Course in PCB Design
Kirsch Mackey, HaSofu

This session will cover the key aspects considered to design a printed circuit board for manufacturing, signal integrity and EMI. We will cover the key design for manufacturing problems and how to fix them, then the key signal integrity and EMI problems, and how those were accounted for in a real-world design by Maxim Integrated’s health monitor design.

The session will have question and answer sections for each major part of the design review and explanation process.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
3:00 p.m. to 5:00 p.m.
40 Proper PCB Layout of DDR2, 3, 4, etc.
Rick Hartley, RHartley Enterprises

The majority of today’s digital systems utilize double data rate (DDR) memory. The advantages are many, mostly that we get twice the amount of information transfer per given “clock frequency.” More data transfer without increased signal integrity or EMI risk: fabulous!

Over the years, guidelines and rules have been developed, attempting to ensure DDR bus structures function as intended. Unfortunately, many rules are overly conservative and require excessive restrictions in PCB layout, adding time and cost to PCB design. Worse, these restrictions can add layers and cost to the PCB itself.

This presentation will focus on identifying reasonable rules and guidelines, as well as proper PCB layout concepts to ensure DDR structures function as intended without adding extra time or cost to the project.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner, Intermediate, Advanced