10:00 a.m. – 5:30 p.m.
1: PCB Design for Engineers
Speaker: Susy Webb, CID, Design Science

This class will feature an overview of the processes of board design from an engineering perspective. To begin, we will discuss how electronics and physics are involved and why controlling rise time, field energy, and transmission lines are important to signals on the board. Placement will be discussed next, with some of those topics including order, flow, and setting up potential routing. The planes and stackup structure play a major role in the quality of the design and impedance control, especially if the design is high-speed, and plane and capacitor placement are a large part of power distribution as well. How signals are routed and their return current is set up is critical to their performance. We will discuss fanouts, using grids, the signal flow from layer to layer, layer-paired routing and spacing. HDI technology is a huge benefit to dense boards, fine-pitch parts and BGAs, so we will go over their setup and routing as well. All these topics will include information on signal integrity, EMI and impedance control, to make a board that works from the beginning. Many aspects of making a board manufacturable also help make it less expensive, so an examination of that will wrap the technical details, followed by information on pros and cons of hand routing vs. autorouting and the quality of board possible with that.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer
Target audience: Beginner, Intermediate

10:00 a.m. – 5:30 p.m.
2: PCB Stackup Design and Materials Selection
Speaker: Bill Hargin, Z-zero

The objective of this tutorial is to guide design teams through the process of evaluating and selecting the right laminate for a design, creating PCB stackups that meet the requirements of complex, multilayer boards that work right the first time, within budget, and with reproducible results across multiple fabricators. The course will go into detail on tradeoffs between loss and cost, including dielectric loss, resistive loss, surface roughness, as well as glass-weave skew. After attending this course, students will be knowledgeable of PCB laminate tradeoffs, the laminate-materials market, and the process of troubleshooting problematic stackup designs. Attendees will also be exposed to cost-effective strategies for controlling loss and glass-weave skew.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate

10:00 a.m. – 12:00 p.m.
4: Differential Pair Routing for SI and EMI Control
Speaker:Rick Hartley, RHartley Enterprises

Differential pairs have been used in PC boards for years to carry high-speed serial and high-speed parallel data in a variety of bus formats. Many board designers and engineers believe the rules for differential pairs are the same in a PCB as they are in cable or twisted pairs of wires. This is usually not the case!

This course will cover the advantages of differential pairs vs. single-ended lines, which differential pair format gives the best impedance control, what is the right spacing between the lines of a pair, crosstalk between differential pairs, what is important in differential pair routing, how much timing skew is really acceptable, the impact of material type and the impact of vias on signal integrity and EMI.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate

10:00 a.m. – 12:00 p.m.
5: From DC to AC – Power Integrity and Decoupling Primer for PCB Designers
Speaker: Ralf Bruening, Zuken

Today, supply voltages decrease with every new silicon generation, contributing as well to the goal of reducing power consumption of electronics. This and the resulting shrinking noise margins for these ICs define increasing demands for the quality and stability of power distribution systems of the PCBs. Shrinking form factors with decreasing board real estate (e.g., IoT devices) and emerging technologies (e.g., autonomous driving, advanced communication units) add fuel to the fire. Hence tighter requirements and constraints from silicon vendors are defined for the power distribution networks (PDN) PCB designers have to follow and implement in conjunction with tighter decoupling schemes. Application-dependent restrictions (e.g., discrete package allowance in automotive) and stringent cost and quality demands further complicate the game.
In this two-hour workshop, the requirements and the basics of PCB power distribution systems are explained in detail. Plate capacitance, loop inductances and cavity resonance are explained without deep math. Side effects to the signal integrity (SI) and EMC behavior of board structures are discussed using illustrated practical examples. The role of decoupling capacitors and their evolution in recent years are a major part of the workshop. Guidelines for a first order covering and resolving power integrity issues are given regardless of the used PCB design and ECAD process. Simulation capabilities addressing power integrity (PI) during PCB design will be explained and demonstrated by animated slides in a generic, vendor-neutral manner as one powerful problem-solving approach for PI issues. Silicon vendor support documents (e.g., design guidelines, constraint-documents, reference designs or spreadsheet tools) to address power integrity are introduced and discussed. Examples from various industries (e.g., automotive) will complement the session with practical application experience.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate

10:00 a.m. – 2:30 p.m.
6: PCB Design for Implementing 3D and High Density Semiconductor Package Technologies
Speaker: Vern Solberg, Solberg Technical Consulting

This tutorial addresses the PCB design and assembly challenges for developing and implementing a broad range of high-density semiconductor package methodologies, including flip-chip and array configured, multiple function 3-D system-in-package (SiP) technologies. T
Topics covered: 1. BGA/CSP process technologies and standards; single die BGA and FBGA packaging, flip-chip and die-size package technologies, wafer level packaging (WLP), fan-out wafer-level packaging (FOWLP), JEDEC package outline standards. 2. Innovative solutions for 2-D, 2.5-D and 3-D packaging, 2-D BGA package technology, 3-D multiple die and stacked package methodologies, implementing 2.5-D for high-density BGA applications, silicon-based interposer structure, glass-based interposer structures, organic (laminate) based interposer structures. 3. Printed circuit board design guidelines for HDI, ball grid array (BGA), fine-pitch ball grid array (FBGA and DSBGA), flip-chip (WLP/FOWLP), 2.5-D interposer structures; 4. HDI circuit and microvia design implementation, HDI circuit fabrication variations, microvia process methodology, design guidelines for HDI circuits, HDI sources and economic issues. 5. Specifying PCB base material, surface finish and coatings, organic-based material selection criteria, specifying thickness of copper foils, surface plating and coating variations, solder mask process considerations; 6. Preparation for high-volume assembly processing, surface mount assembly process overview, basic features needed for SMT assembly processing, system requirements for BGA and CSP device placement, palletizing to maximize assembly process efficiency, assembly process implementation. The material has been developed to better enable the product designer and manufacturing specialist to evaluate a broad number of semiconductor packaging methodologies. Examples shown will furnish both physical and monetary benefits gained using multiple-die packaging, as well as adverse concerns related to supply-chain obstacles and infrastructure limitations.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test Engineer, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced

1:00 p.m. – 4:30 p.m.
7: Circuit Grounding to Control Noise and EMI
Speaker: Rick Hartley, RHartley Enterprises

When time-varying (AC) signals travel in the transmission lines of a board, state-changing electric and magnetic fields are present. These fields, when not controlled, are the source of noise and EMI. In recent years, ICs with very fast rise time outputs have made problems common, even in circuits clocked at low frequencies. Knowing all the basics of proper grounding will help contain and control fields, making noise and EMI issues virtually nonexistent. This 3.5-hour course will focus on the issues PCB designers and engineers need to know to prevent noise, EMI and grounding problems in today’s circuits. We will discuss what is meant by “grounding,” where energy travels in the board, location of high- and low-frequency currents, keys to controlling common mode EMI, cables and other unintended radiators, effects of IC style and packaging on overall grounding, impact of connector pin-out, best locations for IO connectors, divided planes and plane islands in the PCB, routing to control noise, best board stack-ups and filtering of single-ended and differential I/O lines.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Intermediate

1:00 p.m. – 4:30 p.m.
8: The Basics of PCB Fabrication
Speaker: Paul Cooke, AGC

This course will walk the audience through the entire multilayer PCB fabrication process, making stops along the way to explain how the fabricator produces a product to meet the design intent. With ever-decreasing geometries and increased density, today’s PCBs are extremely complex. Fabricators are continually under pressure to keep up with the capabilities needed to produce these types of products. This seminar looks at how a PCB is fabricated and the challenges the fabricator faces to achieve the design intent and meet customer and industry standards. We will examine the processes needed to form microvias, image μBGAs, plate copper in holes the thickness of a human hair and select surface finishes needed for very tight pitch components. The half-day seminar will be interactive with the audience to ensure all questions related to more in-depth PCB fabrication and processes are answered.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, Fabricator Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate

2:30 p.m. – 6:00 p.m.
9: Feeding the Beast: Consumption-Based PCB Design
Speaker: Daniel Beeker, NXP Semiconductor

A step-by-step guideline for determining the PCB design requirements based on device energy consumption requirements. Wave cycle times and transmission line capacity form the basis of this philosophy. The course will center on the LS1043 Network processor, with a focus on the core power supply requirements (7 A/[U]S). The session will begin with a review of EM field behavior and transmission line design, then will outline a process for analyzing the real power delivery challenge posed by a high-performance microprocessor. Starting with the DC current specification, we will use the device package pinout to determine the necessary PCB networks required to support the delivery of power to the device. The package pinout and clock frequency will be used to determine the real “coulombs per wave cycle” that the PDN must support. This will then be used to design both local storage requirements and connecting structures. A spreadsheet will be presented for performing quantitative analyses of the transmission line capability based on the impedance and length, determining the number of wave cycles needed to deliver the required charge. This perspective can be used in the initial design phase or to evaluate existing designs. EMC test results from a production design, MPC-LS-VNP-MOD, using this approach, will be presented.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience:  Beginner, Intermediate, Advanced

10:00 a.m. – 12:00 p.m.
10: Routing and Termination to Control Signal Integrity
Speaker:Rick Hartley, RHartley Enterprises

Virtually all ICs used in digital circuits today have very fast rise time outputs. Traces on boards with fast rise and fall times are referred to as high-speed transmission lines. A number of items contribute to signal integrity issues in such lines. One associated set of contributors to SI problems is lack of proper impedance control, termination and routing. Understanding a few simple concepts can take a circuit from failure to success, and understanding the concepts well can dramatically reduce cost and layer count of PCBs. This presentation will focus on identifying when a line is high speed, effect on signal integrity if proper routing is not implemented, cost-effective (free) impedance control, routing schemes that work, when and how to properly terminate a line and best board stack-ups for impedance control, routing control and low cost.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate, Advanced

10:00 a.m. – 12:00 p.m.
11: PCB Design Techniques to Improve ESD Robustness
Speaker:Daniel Beeker, NXP Semiconductor

Raise the shields, Scotty! Starting with some simple definitions for ESD/EOS, this session describes the important differences in the energy involved and the type of damage that can result. The presentation focuses on PCB design techniques as a means of improving system robustness.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Intermediate

10:00 a.m. – 12:00 p.m.
12: PCB Antennas 101
Speaker: Ben Jordan

This introductory course is specifically about PCB antennas for RF and microwave. It is designed to help develop the basic understanding of antenna principles and how those can be realized on the printed circuit board design. We will discuss the most frequently encountered types of antennas, their radiation patterns, and impedance matching techniques. There will be some in-room demos of ISM band antennas commonly used for Wifi and Bluetooth. We will also introduce the pros and cons of the different types, as well as an awareness of band names and ranges.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate, Advanced

10:00 a.m. – 5:00 p.m.
13: Getting to 56Gb/s
Speaker:Lee Ritchey, Speeding Edge

This course covers all the technical issues involved in the design of very high-speed differential pair signal paths. This is a thorough treatment of the topics to consider to be successful as the speeds of differential pair signal paths increase. 56Gb/s signaling is being shipped in high-performance servers, routers and switches. When data rates exceed 56Gb/s, a number of areas need to be managed that were not significant issues at lower data rates. Among these are the type of glass weave used in laminates, the surface finish on the copper used for signal layers and the loss characteristics of the laminate itself. Effects of vias and other drilled holes can have a significant effect on signal quality if not properly managed. This course will draw on more than 30 test PCBs built to determine the properties of new laminate systems as well as to measure the effects of vias, plane crossings and other features that might affect high speed signals.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, IC Packaging Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate, Advanced

1:30 p.m. – 5:00 p.m.
14: RF and Mixed Signal PCB Layout
Speaker: Rick Hartley, RHartley Enterprises

This session is intended for board designers to understand the things RF engineers request during PCB layout. Experienced RF engineers will likely not learn anything new from this course, as the material is mainly geared to board designers.

Due to sensitivity in analog circuits, the keys to full functionality (whether you are designing very high-frequency analog PCBs, mixing RF with digital, or mixing low-frequency analog with digital) are signal integrity and noise control in the design of the printed circuit board. This course will cover differences between analog and digital, circuit changes over time, lumped vs. distributed length lines, reflections/return loss/VSWR, low- and high-frequency current, transmission line behavior, impedance control, microstrip vs. stripline, coplanar waveguide with ground, circuit termination, 1/4 wavelength couplers and filters designed into board copper, layout techniques and strategies, critical routing and circuit isolation, ground plane splitting (when to and when not to), mismatched loads and other discontinuities, signal splitters, tuning transmission lines, power bus decoupling for RF vs. digital circuits and board stackups for mixed RF and digital circuits.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate

1:30 p.m. – 5:00 p.m.
15: Placement Choices and Consequences
Speaker: Susy Webb, CID, Design Science

There are many ways to place parts on any board, but some work much better for physics, electrical and mechanical purposes. If a new board works electrically but won’t interface properly with the rest of its system, it may require costly and time-consuming redesign and retesting. Designers must understand the board, electrical and system needs, as well as typical placement and routing guidelines and the consequences of not adhering to them. When the reasoning and effects they have on one another are understood, designers will intuitively make good decisions for their board designs and avoid problems. In this presentation, we will discuss choosing effective parts, approximate order of overall placement, placement to set up routing, board and system consequences, manufacturability, and more.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer
Target audience:  Intermediate

1:30 p.m. – 5:30 p.m.
16: The Printed Board Process for Beginners
Speaker:Gary Ferrari, EPTAC

Today’s printed boards are quite complex, demanding many new or enhanced fabrication processes. This course will provide a detailed description of the fabrication process, with a special look at how specific design decisions affect the manufacturability of the printed board. Actual panels taken from each fabrication process will be reviewed and discussed. The seminar concludes with a pictorial slide show illustrating all the processes used to create a multilayer printed board. Attendees will learn PCB manufacturing process steps; material selection; small hole technology; wet processing (imaging, etching and plating); how design decisions affect PCB manufacturing; and cost drivers.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced

10:00 a.m. – 11:00 a.m.
F1: Advancements in Prepreg Enabling New Applications for Millimeter-wave and High Speed Digital
Speaker: John Coonrod, Rogers Corp.

Prepregs or bonding materials are the backbone of most PCB applications. Most recent PCB applications are multilayer, with a desire to get the most functionality from a PCB. The prepregs and bonding materials are the glue that holds together the multilayer circuit structure. To have high functionality, these multilayer PCBs often have layers within the circuit that have very different electrical functions. Some layers of the PCB will be for RF signal processing; other layers may be used for high-speed digital, and some layers may be non-critical for electrical performance and simply make connections or are ground and power planes. It can be difficult to find a prepreg that meets the needs of many PCB fabrication concerns, as well as have the necessary properties to support the demands of RF, microwave, millimeter-wave and high-speed digital (HSD) applications. This presentation begins with an introduction and overview of a new prepreg that meets the many requirements of fabrication and electrical performance for multilayer PCBs used in RF and HSD applications. Some basic fabrication guidelines and capabilities for the prepreg will be given, and following that information there will be data provided showing RF performance. RF performance is related to insertion loss, when using different circuit constructions and showing data up to 80GHz or more. Next will be data sharing, using this prepreg in different HSD constructions. The HSD data are stripline differential pair insertion loss and eye diagrams at different speeds up to 56Gb/s.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator
Target audience:  Beginner, Intermediate

10:00 a.m. – 12:00 p.m.
F2: The 21 Most Common Design Errors Caught by Fabrication (and How to Prevent Them)
Speaker: Ray Fugitt, DownStream Technologies, and David Hoover, TTM

In preparation for this presentation, we talked to many of the largest PCB manufacturers in the US and abroad. We then developed a list of the most common errors found on incoming designs. We started with 10, and based on popular demand, we’ve expanded and keep updating that list! We look at each of the errors and discuss ways to find them before the designs are sent out for manufacturing. Methods we will look at include netlist comparison, design for manufacturing, and design rule analysis. We encourage attendee participation and ask folks to bring their challenges for discussion. After this seminar, the PCB designer will have knowledge to assist them in using their existing tools to produce better and more accurate designs. This year we have asked another FAE to join us with his insights on incoming data as well.

Who should attend:  PCB Designer/Design Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience:  Beginner, Intermediate, Advanced

11:00 a.m. – 12:00 p.m.
F3: Secure Data Exchange Between Design and Manufacturing
Speaker: Michael Ford, Aegis Software, and Hemant Shah, IPC-2581 Consortium

Two fundamental issues of PCB design have remained unresolved for too long. First is the issue of the security of design data as they are passed to manufacturing, where there have been instances of tampering with the intent to introduce vulnerabilities into products. Second, as the technology of inspection and testing of assembled PCBs evolves, detailed design data are needed to facilitate advanced functionality, as well as reduce the programming and preparation time for production. For the first time, both issues are addressed in one solution, with the combination of standards from IPC. In this presentation, we look at the issues around design data management and security, with a focus on how design data, in the form of IPC-2581 (DPMX), are transferred from design, securely across the internet, directly into manufacturing, using IPC-CFX. Once processed by digital manufacturing engineering tools to resolve production BOM and line assignments, the same IPC-2581 file is sent directly to the machines together, with work-instructions ready for advanced programming by the machine vendor in the minimum time. We also look at the reverse flow for DFx, using the same exact secure mechanism that allows designers to understand the potential for design improvement based on actual manufacturing capabilities.

Who should attend:  PCB Designer/Design Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience:  Beginner, Intermediate, Advanced

1:30 p.m. – 2:30 p.m.
F4: Improving Circuit Design and Layout for Accessibility and Success
Speaker: Tomas Chester, Chester Electronic Design

With this seminar, attendees will be given details and examples of additional information that can be embedded within their existing design process. This content is aimed at improving the successful outcome of their design and reducing the time spent acquiring circuit, component, or layout knowledge. Whether you are a solo designer or an engineer within a large team, these design additions will enable participants to look beyond their own immediate workflow and improve the project design process.
The seminar will focus on project foresight, multi-channel/multi-project design reuse, and identical characterization during the entire development cycle.
The following topics will be covered: component/library creation for future/multi-project use, schematic accessibility and complexity reduction, printed circuit schematic and layout design strategies for verification and debug, and procedural interactions of a successful project.
Attendees will gain methods for improving design success: design examples and experience interacting with various project states, methods for reducing verification and debug cycles, and multi-user interactive perspectives.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test Engineer, Assembly Engineer/Operator
Target audience:  Beginner

1:30 p.m. – 2:30 p.m.
F5: Software-First PCBA for Mitigating Risks: Achieving First-Time Right
Speaker: Ryan Saul, Tempo Automation

As businesses return online, engineering teams need creative, efficient ways to solve these problems and develop builds faster, while ensuring quality doesn’t take a backseat. This talk will leverage the speaker’s experience in smart factory operations, PCB assembly and sales engineering to provide insights on today’s electronics manufacturing industry in a coronavirus-impacted world and discuss how engineering teams can remove the risks associated with mission-critical manufacturing by using EMS companies that offer software-first PCBA. The speaker will introduce key cases of how a proprietary software drives the process in a smart, connected factory, automating processes everywhere possible, augmenting human skills in other areas, yielding significant improvements in capacity, throughput and quality, and why this is impactful for project timelines, product quality, and engineering success.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience:  Beginner

2:30 p.m. – 3:30 p.m.
F6: PCB Design Optimization: What it Means and New Methods
Speaker: Zachariah Peterson, Northwest Engineering Solutions

PCB designers often speak of “design optimization,” and causal PCB design optimization has found a stronger mathematical footing in the engineering literature over the last 10 years. In particular, transmission line design requires satisfying multiple design objectives and constraints that may be in conflict, and engineers need tools and methods to help them balance design objectives while staying within their design constraints. For ultra-high-speed boards, designers need to optimize transmission line designs within the relevant signal bandwidth, which can extend to hundreds of GHz. Newer signaling specifications and standards (e.g., USB4, DDR5, and IEEE 802.3 standards) require this level of optimization throughout the signal bandwidth to demonstrate compliance, and design teams need a set of tools that help expedite this type of optimization. Current PCB design optimization methods are typically measurement-based or field-solver-based, but CAD packages lack support for these tasks or for accepted analytical methods in PCB design optimization.

This presentation outlines the current state of PCB design optimization techniques used to produce useful designs, while balancing multiple design goals. An alternative method for design optimization from analytical equations describing transmission lines will be presented. Some practical examples for striplines, microstrips, and mode-selective waveguides will be presented. These models are fully causal and account for dispersion, dielectric losses, skin effect losses, and copper roughness in a real PCB. The presented method is applicable to any transmission line with a known analytical or numerical model, and the method uses standard evolutionary computation techniques to optimize the design. Similar techniques can be implemented in advanced field-solver tools, but designers with basic coding skills can use some simple open-source packages to build their own design optimization routines for transmission lines. Furthermore, the transmission line design optimization method presented here can be used to balance multiple design objectives, which is not currently possible in PCB CAD packages.

Who should attend:  PCB Designer/Design Engineer, System Designer, SI Engineer
Target audience:  Intermediate, Advanced

2:30 p.m. – 3:30 p.m.
F7: PCB Part Shortage Solutions
Speaker: Shane Shuffield and Sebastian Weber, Advanced Assembly

Electronics parts shortages are crippling assembly lines around the world. To help alleviate some of the headaches, two solutions are offered. First, a discussion of benefits and drawbacks of a semi-novel land pattern modification that permits multiple imperial parts sizes to fill the same board space. For example, a hard-to-find 0402 MLCC might be swapped for a 0201 or 0603 package. This has been successfully tested for parts ranging from 0201 to 1205 in size (imperial). Successful test results will be shared during the presentation. Additionally, electrical concerns surrounding the safety of stepping down to smaller land patterns will be discussed. Second, from traditional sources to new-old-stock to gray-market acquisitions, we will discuss the tips and tricks, as well as the trials and tribulations that come with making sure customer orders get out on time with a minimum of overage and wasted product. Attendees will gain a better understanding of the problems assemblers solve every day. The knowledge gained will allow them to save money and time with their next project.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, Other
Target audience:  Beginner

3:30 p.m. – 4:30 p.m.
F8: Electromagnetic Fields for Normal Folks: Show Me the Pictures and Hold the Equations, Please!
Speaker:

The material presented will be focused on the physics of electromagnetic energy basic principles, presented in easy-to-understand language with plenty of diagrams. Attendees will discover how understanding the behavior of EM fields can help design PCBs that will be more robust and have better EMC performance. This is not rocket science, but an easy-to-understand application of PCB geometry. It’s all about the space!

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience:  Beginner

3:30 p.m. – 4:30 p.m.
F9: Design and Analysis of a High-Performance PCB Interposer for 100G PAM4 Validation
Speaker: Xiao Ming Gao, Intel Corp.

In recent years, the explosive growth of data traffic and increased switch bandwidth put demanding throughput requirements on chip to chip and chip to module links in the data center. The 100Gb/s per lane serializer/deserializer (Serdes) IC is the key solution for enabling 200G, 400G, and future 800G Ethernet through lanes aggregation. Traditional non-return to zero (NRZ) signaling is not able to meet 100Gb/s throughput on copper-based interconnect such as Ethernet switches due to excessive wide bandwidth requirements. To overcome this limitation, 4-level Pulse Amplitude Modulation (PAM4) is used as the primary signaling method. PAM4 can double NRZ transfer rate using the same bandwidth by encoding two bits into one symbol compared with 1 bit in NRZ, hence each PAM4 symbol waveform has four voltage levels. Compared with NRZ, eye openings of PAM4 are much smaller and these are further subject to crosstalk and noise impacts. To validate different PAM4 designs from Serdes vendors and evaluate the bit error rate (BER) performance, new platforms must be design and optimized. These not only use extra resources but slow time to market. To address these challenges, a high-performance PCB interposer using coaxial via is designed and analyzed. This architecture has the advantage of evaluating different PAM4 Serdes performance without redesigning the validation platform and therefore can significantly reduce the development cost, accelerate the validation process, and improve the time to market. To improve the interposer performance on PAM4 100Gb/s signaling, it uses the coaxial via-based microstrip line for high-speed signal routings. Different from regular through-hole signal vias that require additional multiple surrounding ground vias, the coaxial via has a built-in shielding wall around the signal. This not only significantly saves routing space but drastically reduces crosstalk introduced by nearby signals coupling and therefore improves PAM4 voltage margins and BER performance. The coaxial via can be easily manufactured with the current PCB fabrication process using sequential multiple drill processes. The interposer channel simulation is illustrated, and results demonstrate the interposer can achieve 100G PAM4 signaling with the BER better than 10-12.

Who should attend:  PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience:  Intermediate, Advanced

10:00 a.m. – 12:00 p.m.
17: PCB Layout of Switch Mode Power Supplies
Speaker: Rick Hartley, RHartley Enterprises

When executing PCB layout, we tend to treat digital circuits differently from analog circuits. Each has its own critical requirements. Switch mode power supplies are another wrinkle altogether, and usually need to be treated differently from either. All switch mode power supplies have four to five circuit loops, all of which are important, but a couple of these loops are downright critical in terms of PCB layout. An improperly designed switch mode supply will often not function as intended, and in some cases will not function at all. In contrast, understanding what makes up a switcher circuit and knowing how to take care of the loops during board layout will permit these supplies to operate flawlessly with very high efficiency.
This two-hour course will outline the difference between switchers and series-regulated power supplies, the different types of switcher circuits (buck, boost, etc.), basic theory of operation of switcher circuits and the impact of the various components, definition and behavior of the five loops, layout to isolate loops from one another, minimize voltage drop, and control current paths, layout to minimize noise and EMI, effect of paralleling output capacitors and proper grounding technique.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced

10:00 a.m. – 12:00 p.m.
18: An Intuitive Approach to Understanding Basic High-Speed Layout
Speaker:Keven Coates, Fluidity Technologies

What is a wire? At high speeds, it behaves very differently from what we were taught in college. This presentation on high-speed basics makes the subject intuitive in a way that’s easily understood. Learn about how frequency enters the picture, high-speed signal propagation, impedance, noise, and reflections with easy-to-understand animations and analogies to understand this subject on a deeper level.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner

10:00 a.m. – 12:00 p.m.
19: Ask the Flexperts with Lessons Learned
Speaker: Mark Finstad, Flexible Circuit Technologies and Nick Koop, TTM Technologies

This course will cover the entire gamut of flexible and rigid-flex circuits from two of the most recognized names in the flexible circuit industry: Mark Finstad (co-chair of IPC-2223) and Nick Koop (co-chair of IPC-6013). Topics covered will include mechanical design/material selection, cost drivers, bending and forming concerns, testing, and issues unique to rigid-flex. This course also includes a complete virtual plant tour of a flexible circuit manufacturing facility to help attendees understand the manufacturing processes. Throughout the presentation, the instructors will share real-life stories of flexible circuit applications gained over 35+ years in the industry. Some are success stories, others not so much, but all provide excellent lessons learned. The instructors also welcome and encourage questions and enjoy wandering off-course with lively interactive discussions on specific topics from the class.

Who should attend: PCB Designer/Design Engineer, System Designer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Intermediate, Advanced

10:00 a.m. – 2:30 p.m.
20: Effective PCB Design: Techniques to Improve Performance
Speaker: Daniel Beeker, NXP Semiconductor

As IC geometries continue to shrink and switching speeds increase, designing electromagnetic systems and printed circuit boards to meet the required signal integrity and EMC specifications has become even more challenging. A new design methodology is required. Specifically, the utilization of an electromagnetic physics-based design methodology to control the field energy in your design will be discussed. This training module will walk through the development process and provide guidelines for building successful, cost-effective printed circuit boards.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Intermediate

10:00 a.m. – 2:30 p.m.
21: Designing the Signal Return Path
Speaker: Susy Webb, CID, Design Science

When designing a board, signal routing and its return are critical to the circuit working properly. Great care is usually given to routing the signals, but often the return portion is the last thing considered, and sometimes forgotten altogether. This presentation will talk about the importance of designing that return path, with a discussion of the physics involved, where the energy flows, the interference caused when it is not controlled, and the planes and stackup needed. Additionally, we will discuss the best ways to contain energy fields, the spacing that helps prevent problems, and the routing and return movement from layer to layer. Throughout, we will discuss some signal routes and look at the paths that might set up the best possibility for a clean return.

Who should attend: PCB Designer/Design Engineer
Target audience: Intermediate

10:00 a.m. – 4:30 p.m.
22: Printed Circuit Board Stackup Design for High Performance Product
Speaker: Lee Ritchey, Speeding Edge

This comprehensive seminar explains how to design a PCB stackup to optimize performance, while attaining the lowest cost possible. With the advent of very-high-speed signaling, along with multiple very-high-current power supply rails, it is necessary to understand how materials behave and how PCBs are fabricated in order to arrive at a PCB stackup that results in a “right the first time” design.
The seminar draws from the speaker’s long experience designing PCB stackup for products ranging from video games to super computers. It draws on the results of dozens of test PCBs used to characterize materials from a loss and high-speed skew perspective.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced

10:00 a.m. – 6:00 p.m.
23: PCB 102 – Advanced Process Engineering Defects
Speaker: Paul Cooke, AGC

This course will walk the audience through the entire multilayer PCB fabrication process, making stops along the way to explain how PCB design plays into the numerous fabrication steps and if the finished product can meet the intended quality and reliability requirements. A detailed explanation will be given for each of the process steps and how that step affects quality and reliability. The design requirements will also be discussed and an explanation as to the dos and don’ts of how it can affect the fabrication and how it impacts yields. The course will also look at pros and cons of variables available to the designer, resin system, plating, solder mask, surface finish, materials selection, copper weights, feature size, etc. The course also looks at fabrication drawings, specifications, and how they affect yield, cost, quality and reliability. As we look at each process, we will examine the challenges faced by the fabricator and what they need to do to ensure the customer receives a product that meets the design intent and specifications as listed on the purchase order. We will look at new materials, processes for more complex designs, and how the fabricator adjusts their process to minimize the risk of defects. As we talk about potential defects, we will look at detection methods and process controls to ensure the highest level of quality.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, Other
Target audience: Intermediate, Advanced

1:00 p.m. – 4:30 p.m.
24: Heat Management for SMD, LED, and Systems 1W to 50W
Speaker:Keven Coates, Fluidity Technologies

Do you use power MOSFETs, high power LEDs, power resistors, or hot processors in your design and want to avoid heat-related system failures? This course covers the best options for you to manage heat cost effectively and reliably. It gives a good overview of PCB design to maximize SMD/LED heat dissipation. It also covers how to choose the right heat sink interface materials, heat sink designs, natural and forced airflow options, as well as heat dissipation simulations (both mechanical and in software). We’ll go over some helpful tools, and break down thermal resistance equations to simple terms. Heat management doesn’t have to be scary. Take this class to know your options. Now with LED specifics!

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner, Intermediate, Advanced

1:00 p.m. – 4:30 p.m.
25: Flexible and Rigid Flex Circuit Design Principles
Speaker: Vern Solberg, Solberg Technical Consulting

This tutorial has been developed to furnish the design professionals, systems engineers and assembly and test engineering specialists with a thorough understanding of the materials, fabrication process variations and preferred design practices for flexible and rigid-flex circuits, the requirements for automated SMT assembly and will include detailed discussion regarding panel planning and assembly process variations. Throughout this program, the presenter will be referencing guidance furnished in the latest revisions of IPC-2222, Sectional Design Standard for Rigid Organic Printed Boards and IPC-2223, Sectional Design Standard for Flexible Printed Boards, and include base material selection, fabrication process variations and provisions necessary for robotic assembly processing. Specific topics of discussion: 1. Applications and use environment (commercial/consumer, industrial/automotive, medical/aerospace); 2. Material and SMT components; base material and metallization technologies; selection criteria for SMT components; SMT land pattern development; 3. Flexible and rigid-flex circuit design principles; flex circuit outline planning; circuit routing and interconnect methodologies; SMT land pattern reinforcement methodologies; 4. Assembly processing of flex and rigid-flex circuits; dimensioning and tolerance criteria; SMT assembly process variations and methodologies; palletized layout for inline assembly processing.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test Engineer, Assembly Engineer/Operator
Target audience:  Beginner, Intermediate, Advanced

2:30 p.m. – 4:30 p.m.
26: IPC-DPMX’s Bi-directional electronically executable DFM exchange accelerates NPI
Speaker: Hemant Shah, IPC-2581 Consortium, and Dana Korf, Korf Consultancy

What’s new in revision C of IPC Digital Product Model Exchange (DPMX, aka IPC-2581)? Digital Product Model Exchange (a new name for Generic Requirement for Printed Board Assembly Product Manufacturing Description Data and Transfer Methodology) introduces new features, automation supporting Industry 4.0, and bidirectional DfX intelligence capability that eliminates the back and forth between designers and manufacturers before production begins. Revision C includes the bidirectional DfX data exchange through which feedback between design and manufacturing is conveyed and tracked before manufacturing begins. DfM checking and resolution can be a frustrating and time-consuming process that poses little overall benefit for customers. IPC-2581C addresses the need for a collaborative, executable exchange for DfM issues, eliminating spreadsheets, PowerPoints and emails, and accelerating new product introduction. IPC-2581C is also a major component of the digital twin architecture and strategy, setting the standard for interoperability between different digital twin solutions, bringing maximum value from data. This two-hour workshop will provide a brief overview of IPC-2581, particularly revision C; how to generate IPC-2581 files from PCB design software; various function modes supported by IPC-2581; what’s new in revision C at a “high level”; and the benefits to designers and manufacturers.

Who should attend: PCB Designer/Design Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Intermediate, Advanced

2:30 p.m. – 6:00 p.m.
27: PC Board Design of Power Distribution and Decoupling
Speaker: Rick Hartley, RHartley Enterprises

Power distribution in PCBs is the foundation around which all things work in the circuit. If this is not designed correctly, the entire circuit is at risk from noise and signal integrity issues, to say nothing of the severely increased possibilities of EMI. Low impedance in the structure, across the harmonic frequency range of a digital circuit is critical. A number of subtle layout techniques will have major impact on power bus impedance, inductance in particular. This 3.5-hour course will cover power bus target impedance, inductance of vias, planes and capacitors, mounting inductance of capacitors, energy delivery to IC cores, the “Bandini Mountain,” best mounting of capacitors based on board stack-up, the importance of IC pinout, placement of decoupling in both low-layer-count and high-layer-count boards, real performance of capacitors (vs. myth), how much decoupling, multiple capacitor values, how to minimize anti-resonant peaks, ferrites in the power bus, analog and RF decoupling, the importance of power/ground plane pairs, ultra-thin power and ground plane pairs and the importance of board stack.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Intermediate, Advanced

2:30 p.m. – 6:00 p.m.
28: Design for Solvability, Performance and Manufacturing
Speaker:Michael R. Creeden, CID+, Insulectro

Attendees will receive an understanding of electromagnetic theory/application with a strong emphasis on material and process solutions that help routing application. This starts with data capture, rules definition and tool automation, and covers routing perspectives from the start of the layout cycle to the review and verification stages, to generation of deliverables for manufacturing. Emphasis is on the role that EM fields play to manage a circuit to be cost-effective, perform well electrically and be a reliable, high-yield product. We will touch on all types of circuit technologies in many market segments. The focus is on integration between design and manufacturing early in the development cycle, to build a product that is correct-by-construction and performs on Revision-1. We will cover a range of topics, including hybrid material selection for rigid and rigid-flex; rationale for considering HDI; placement, routing techniques, power delivery, EMI shielding; technological challenges from design through manufacturing process. Students will learn what it takes to successfully implement these concerns: complex solvability; high-speed, RF and thermal performance; high-yield and reliable manufacturability.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator
Target audience:  Advanced

10:00 a.m. – 12:00 p.m.
29: Signal Attenuation in Very High-Speed Circuits
Speaker: Rick Hartley, RHartley Enterprises

In all high-speed/high-frequency circuits, signal integrity is dependent on a number of variables, all of which accumulate to impact the noise budget of the circuit. With very high-speed circuits, an even larger number of issues comes into play, and all the effects are more extreme. Some problems are driven by design deficiencies, some by the physical structure and design of the ICs, and still more are driven by the PCB copper style and base material parameters.
This course will outline all the effects impacting signal integrity at very high speeds and will detail such items as via stubs, jitter, inter symbol interference, impact of copper style on skin effect, loss tangent, impact of layer change during routing and other major signal integrity concerns, as well as the impact some of these items have on timing and Y-axis attenuation of signal eyes. Also discussed will be solutions to these issues, including some new high-speed base materials.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced

10:00 a.m. – 4:30 p.m.
30: Power Delivery System Design
Speaker: Lee Ritchey, Speeding Edge

With the advent of ICs with multiple power rails at very high currents, the design of the power delivery system in a modern product is often more difficult than routing the PCB to ensure good signal integrity. The power delivery system must deliver power to devices at frequencies from D to hundreds of megahertz. The application notes that accompany most ICs do not contain adequate information to allow a designer to correctly design the PDS.
This all-day course is aimed at providing the information needed to get the job done right. It draws on the speaker’s experience designing hundreds of power delivery systems for products ranging from satellites to super computers. It contains a very large number of test PCBs used to determine how well each component will perform when used in a PDS.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced

1:00 p.m. – 4:30 p.m.
31: PC Board Design for Optimum Fabrication and Assembly
Speaker:Rick Hartley, RHartley Enterprises

Many engineers believe the cost of bare boards and assemblies is purely a function of board size, thickness, number of layers, spacing between features, etc. Part of that statement is true, but certainly not all of it. Many things drive cost of both. More important, many PCB design issues determine the quality of both bare boards and assemblies, such as where copper is located and its density, part placement, how the board is routed, balanced PCB stack-up, feature sizes, etc.
This 3.5-hour session will focus on how to accomplish the goal of both low cost and high quality with just a few simple concepts. Bottom line: When boards are not designed properly, fabricators and assemblers must make modifications to the design to produce them. Sometimes their modifications cause the boards to malfunction. If we design correctly, this will not happen.

Who should attend:  PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner, Intermediate